Report generated on 06-May-2025 at 21:45:06 by pytest-html v3.2.0
1483 tests ran in 3632.31 seconds.
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1326 passed, 0 skipped, 157 failed, 0 errors, 0 expected failures, 0 unexpected passes| Result | Test | TIDL Subgraphs | Complete TIDL Offload | Duration | Links |
|---|---|---|---|---|---|
| No results found. Try to check the filters | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_505] | 1 | True | 0.59 | |
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[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_505' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_505', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-1' pid=2855506 parent=2853913 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d6f9000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.44225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.44276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.44302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.44341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.44366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.44390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.44418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.44446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.44472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.44498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.44521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.44549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.44580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.44609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.44634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.44662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.44690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.44721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.44750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.44776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.44809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.44841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.44868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.44890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.44918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.44940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.44967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.44999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.45023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.45052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.45080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.45107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.45141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.45170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.45191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.45222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.45250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.45272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.45300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.45333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.45336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.45339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.591164228369427 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089968 bytes MEM: Free's : 26 free's of 25089968 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.591164228369427 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_215] | 1 | True | 600.11 | |
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[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_215' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_215', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): > os.remove(f) E FileNotFoundError: [Errno 2] No such file or directory: '/dev/shm/vashm_buff_APHlf3_0' test_tidl_unit.py:121: FileNotFoundError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884ce700 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.42136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.43308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.43343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.43384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.43411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.43442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.43477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.43538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.43567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.43596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.43623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.43649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.43676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.43699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.43726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.43756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.43780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.43809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.43840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.43864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.43893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.43922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.43951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.43979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.44006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.44028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.44052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.44083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.44108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.44129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.44156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.44184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.44206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.44235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.44256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.44281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.44306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.44337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.44358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.44388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.44415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.44446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.44449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.44451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.90217s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.90229s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.90235s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.90236s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.90238s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.90240s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.90242s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_597] | 1 | True | 600.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_597' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_597', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: -15 E assert -15 == 0 E + where -15 = <Process name='Process-1' pid=2855521 parent=2854366 stopped exitcode=-SIGTERM>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b18650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.85545s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.85553s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.85561s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.85562s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.85564s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.85566s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.85568s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1167] | 1 | True | 0.37 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1167' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1167', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-2' pid=2856919 parent=2853916 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae800421870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Convolution_1167/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_131] | 1 | True | 600.12 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_131' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_131', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-2' pid=2858141 parent=2853904 started>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6c255c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12047s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.23031s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.23047s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.23057s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.23058s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.23060s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.23064s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.23067s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_107] | 1 | True | 600.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_107' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_107', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-4' pid=2858487 parent=2853916 started>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008d8b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.9736s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.9754s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.9763s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.9764s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.9766s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.9768s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.9770s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_167] | 1 | True | 600.12 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_167' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_167', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-3' pid=2859031 parent=2854694 started>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e63fa10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5635s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.13745s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.13752s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.13759s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.13761s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.13762s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.13765s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.13766s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_565] | 1 | True | 600.10 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_565' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_565', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-6' pid=2859099 parent=2854728 started>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda775eeca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.14099s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.14107s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.14114s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.14116s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.14117s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.14120s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.14123s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_816] | 1 | True | 600.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_816' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_816', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-4' pid=2860111 parent=2854565 started>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090cebca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5987s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12444s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12457s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12465s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12466s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12468s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12470s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12472s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_829] | 1 | True | 600.10 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_829' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_829', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-5' pid=2860792 parent=2853910 started>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1990f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4267s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.16235s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.16250s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.16259s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.16260s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.16262s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.16264s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.16265s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_912] | 1 | True | 600.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_912' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_912', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-2' pid=2861074 parent=2853924 started>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40ec010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7719s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7726s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7727s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7732s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7734s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7736s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7738s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1410] | 1 | True | 600.10 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1410' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1410', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-5' pid=2861140 parent=2853913 started>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466b493570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21222s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.53986s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.54001s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.54009s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.54010s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.54011s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.54013s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.54015s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_561] | 1 | True | 600.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_561' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_561', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-11' pid=2861536 parent=2853901 started>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6bade0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1753s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.14269s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.14276s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.14282s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.14284s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.14285s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.14288s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.14290s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_306] | 1 | True | 0.18 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_306' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_306', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-13' pid=2861625 parent=2854029 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece810c3d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6163618249394605 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39548757 bytes MEM: Free's : 26 free's of 39548757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6163618249394605 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1129] | 1 | True | 600.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1129' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1129', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-10' pid=2862041 parent=2854331 started>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2e1f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.15523s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.15536s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.15543s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.15545s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.15546s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.15550s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.15553s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_54] | 1 | True | 0.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_54' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_54', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-12' pid=2862221 parent=2853907 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4633180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53911925 bytes MEM: Free's : 26 free's of 53911925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 16, 108, 108) got (4, 16, 105, 105) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_423] | 1 | True | 0.15 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_423' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_423', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=2862462 parent=2853993 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0088bc70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3214s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3217s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5319246708944892 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30717357 bytes MEM: Free's : 26 free's of 30717357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5319246708944892 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_405] | 1 | True | 600.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_405' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_405', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-16' pid=2863102 parent=2854095 started>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af34e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.20290s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.20304s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.20313s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.20315s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.20317s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.20320s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.20322s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1432] | 1 | True | 600.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1432' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1432', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-9' pid=2863322 parent=2853993 started>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008d3340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12635s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12642s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12647s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12649s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12650s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12651s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12652s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1309] | 1 | True | 600.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1309' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1309', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-6' pid=2863889 parent=2854130 started>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237bdae40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2250s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6488s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6496s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6502s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6504s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6506s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6509s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6511s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_402] | 1 | True | 600.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_402' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_402', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-7' pid=2864467 parent=2854468 started>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48eeef70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12406s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12419s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12429s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12431s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12433s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12436s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12438s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_941] | 1 | True | 600.10 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_941' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_941', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-5' pid=2865188 parent=2853959 started>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a8a9040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5425s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5428s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5433s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5434s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5435s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5437s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5439s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_557] | 1 | True | 600.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_557' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_557', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-8' pid=2865496 parent=2854326 started>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a0d3dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3828s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3833s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3835s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3840s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3841s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3843s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3845s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_637] | 1 | True | 600.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_637' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_637', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-32' pid=2865854 parent=2854029 started>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7e11460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12547s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12552s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12553s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12558s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12559s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12561s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12562s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_199] | 1 | True | 600.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_199' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_199', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-20' pid=2866073 parent=2853921 started>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436305d0b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4862s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4868s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4869s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4873s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4874s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4876s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4878s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_310] | 1 | True | 0.28 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_310' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_310', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-4' pid=2866732 parent=2854890 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b9d030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 172822453 bytes MEM: Free's : 26 free's of 172822453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 236, 88, 88) got (4, 236, 86, 86) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_553] | 1 | True | 600.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_553' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_553', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-13' pid=2867148 parent=2854291 started>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164dafaf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4023s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4029s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4030s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4034s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4036s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4038s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4040s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_482] | 1 | True | 600.10 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_482' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_482', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-26' pid=2867528 parent=2854164 started>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e72f2f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4259s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4264s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4268s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4270s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4271s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4273s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4274s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_920] | 1 | True | 600.10 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_920' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_920', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-16' pid=2867853 parent=2854890 started>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686824d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1281s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.13001s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.13007s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.13008s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.13012s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.13013s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.13015s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.13016s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_334] | 1 | True | 0.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_334' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_334', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-33' pid=2868473 parent=2853907 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45b67c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.173s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.204703882957815e+65 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17876677 bytes MEM: Free's : 26 free's of 17876677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 5.204703882957815e+65 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_661] | 1 | True | 600.01 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_661' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_661', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-43' pid=2869045 parent=2853907 started>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46b7fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5700s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.30476s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.30486s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.30497s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.30499s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.30502s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.30506s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.30509s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_325] | 1 | True | 600.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_325' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_325', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-3' pid=2870206 parent=2853904 started>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6ed7a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.10569s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.10575s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.10579s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.10581s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.10582s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.10583s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.10584s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1292] | 1 | True | 0.11 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1292' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1292', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-7' pid=2870490 parent=2854728 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77633df0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5521176327309638 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27013637 bytes MEM: Free's : 26 free's of 27013637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5521176327309638 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_330] | 1 | True | 600.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_330' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_330', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-6' pid=2870752 parent=2854694 started>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e689ea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5106s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5113s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5114s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5118s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5119s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5121s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5123s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_441] | 1 | True | 600.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_441' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_441', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-10' pid=2870907 parent=2853916 started>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8007e6750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5546s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5553s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5559s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5560s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5561s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5563s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5565s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_826] | 1 | True | 600.10 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_826' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_826', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-6' pid=2871361 parent=2853913 started>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d465b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7794s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7818s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7826s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7827s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7829s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7831s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7833s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1303] | 1 | True | 600.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1303' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1303', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-13' pid=2871930 parent=2853901 started>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da8c3e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7493s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7500s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7506s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7507s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7508s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7511s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7512s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1297] | 1 | True | 0.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1297' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1297', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=2873180 parent=2854095 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae917c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5441991308989202 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19037645 bytes MEM: Free's : 26 free's of 19037645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5441991308989202 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_355] | 1 | True | 600.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_355' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_355', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-13' pid=2873488 parent=2854331 started>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc243490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6920s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6927s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6928s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6934s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6935s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6937s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6939s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_407] | 1 | True | 600.11 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_407' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_407', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-20' pid=2873683 parent=2854728 started>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77737cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1500s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.10533s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.10545s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.10553s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.10554s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.10556s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.10558s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.10560s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_525] | 1 | True | 0.08 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_525' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_525', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=2874446 parent=2853924 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4180330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8192259094514135 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19388101 bytes MEM: Free's : 26 free's of 19388101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8192259094514135 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_945] | 1 | True | 600.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_945' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_945', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-24' pid=2875365 parent=2854095 started>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aea2690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.8920s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.8925s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.8931s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.8932s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.8934s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.8936s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.8938s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1405] | 1 | True | 600.10 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1405' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1405', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-17' pid=2876153 parent=2853910 started>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1f3530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.18583s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.18590s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.18592s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.18598s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.18599s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.18601s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.18603s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1334] | 1 | True | 600.10 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1334' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1334', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-12' pid=2876412 parent=2854463 started>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883ddd90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5958s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.13783s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.13792s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.13800s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.13801s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.13803s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.13805s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.13807s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_509] | 1 | True | 0.13 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_509' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_509', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-9' pid=2876477 parent=2853959 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451aab7d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5826199506917645 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33464941 bytes MEM: Free's : 26 free's of 33464941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5826199506917645 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_501] | 1 | True | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_501' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_501', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-17' pid=2876916 parent=2854468 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f4c920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1254s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6472722809780196 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68459837 bytes MEM: Free's : 26 free's of 68459837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6472722809780196 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_849] | 1 | True | 600.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_849' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_849', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-19' pid=2878897 parent=2854326 started>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a212470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12705s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12712s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12718s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12719s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12720s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12722s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12724s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_813] | 1 | True | 600.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_813' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_813', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-36' pid=2879423 parent=2854029 started>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8177460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.18906s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.18919s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.18928s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.18930s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.18931s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.18933s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.18935s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_541] | 1 | True | 600.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_541' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_541', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-17' pid=2879641 parent=2854130 started>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d20e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.23505s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.23514s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.23523s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.23524s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.23526s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.23528s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.23531s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_793] | 1 | True | 0.13 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_793' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_793', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=2879845 parent=2854468 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e714c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5356951433349472 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31571309 bytes MEM: Free's : 26 free's of 31571309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5356951433349472 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_593] | 1 | True | 600.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_593' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_593', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-28' pid=2880128 parent=2854468 started>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f5d430 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.18604s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.18621s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.18630s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.18632s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.18633s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.18636s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.18638s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_404] | 1 | True | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_404' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_404', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-19' pid=2882357 parent=2853993 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008e9a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33868229 bytes MEM: Free's : 26 free's of 33868229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (24, 131, 131) got (24, 128, 128) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_808] | 1 | True | 600.01 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_808' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_808', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-16' pid=2882601 parent=2854366 started>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b7b330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7695s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7702s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7704s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7709s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7711s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7713s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7715s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_179] | 1 | True | 600.10 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_179' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_179', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-28' pid=2883236 parent=2854164 started>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e862b10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.14658s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.14705s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.14719s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.14721s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.14724s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.14735s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.14966s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_452] | 1 | True | 600.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_452' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_452', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-33' pid=2883389 parent=2854565 started>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d647d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.8528s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.8532s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.8536s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.8536s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.8538s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.8539s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.8541s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_287] | 1 | True | 600.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_287' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_287', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-23' pid=2883390 parent=2854291 started>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164b1f380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4134s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4140s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4146s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4147s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4148s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4149s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4151s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_337] | 1 | True | 600.11 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_337' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_337', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-50' pid=2883608 parent=2853921 started>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631b5b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6733s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6742s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6743s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6751s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6752s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6754s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6756s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_374] | 1 | True | 600.10 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_374' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_374', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-21' pid=2884371 parent=2854890 started>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b196b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4140s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4146s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4148s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4152s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4154s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4156s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4157s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1053] | 1 | True | 600.10 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1053' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1053', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-33' pid=2884503 parent=2853959 started>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a837180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1308s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4980s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4997s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4998s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5003s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5004s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5006s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5007s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1110] | 1 | True | 0.07 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1110' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1110', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-39' pid=2884725 parent=2853924 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40918d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7035066989798033 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13111237 bytes MEM: Free's : 26 free's of 13111237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7035066989798033 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_369] | 1 | True | 600.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_369' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_369', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-45' pid=2885967 parent=2853924 started>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb409aea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1283s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3487s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3492s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3493s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3497s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3498s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3500s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3501s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_251] | 1 | True | 600.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_251' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_251', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-42' pid=2886604 parent=2853993 started>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00526c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5022s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5042s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5044s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5048s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5049s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5050s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5052s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_70] | 1 | True | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_70' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_70', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-55' pid=2886935 parent=2853907 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46c8f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65671793 bytes MEM: Free's : 26 free's of 65671793 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 35, 108, 106) got (4, 35, 105, 105) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_625] | 1 | True | 600.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_625' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_625', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-70' pid=2887873 parent=2853907 started>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4339330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.11551s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.11556s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.11557s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.11561s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.11562s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.11564s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.11565s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1408] | 1 | True | 600.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1408' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1408', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-4' pid=2888500 parent=2853904 started>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6edcf40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7883s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7888s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7892s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7893s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7894s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7896s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7897s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_589] | 1 | True | 600.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_589' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_589', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-11' pid=2888704 parent=2853916 started>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008d3260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.17545s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.17564s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.17574s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.17576s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.17578s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.17581s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.17583s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_83] | 1 | True | 600.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_83' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_83', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-11' pid=2888769 parent=2854694 started>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6984d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.52s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.53s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3407s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3412s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3416s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3417s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3418s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3419s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3420s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_944] | 1 | True | 600.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_944' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_944', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-18' pid=2889214 parent=2853901 started>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da622b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4096s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4102s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4103s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4106s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4107s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4109s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4110s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_545] | 1 | True | 600.10 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_545' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_545', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-21' pid=2889412 parent=2854728 started>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77738760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7316s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7337s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7343s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7344s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7346s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7348s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7350s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_315] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_315' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_315', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-21' pid=2890289 parent=2854331 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc339b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20391957 bytes MEM: Free's : 26 free's of 20391957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (2, 32, 70, 70) got (2, 32, 64, 64) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_521] | 1 | True | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_521' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_521', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=2890598 parent=2854331 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc344e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5923959023202358 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77512101 bytes MEM: Free's : 26 free's of 77512101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5923959023202358 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_307] | 1 | True | 600.10 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_307' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_307', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-22' pid=2891587 parent=2854463 started>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883f2900 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1478s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7695s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7721s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7727s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7728s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7729s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7732s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7733s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_66] | 1 | True | 0.60 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_66' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_66', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-32' pid=2892080 parent=2854331 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3592f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.62s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 207429525 bytes MEM: Free's : 26 free's of 207429525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 184, 106, 108) got (4, 184, 105, 105) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_127] | 1 | True | 600.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_127' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_127', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-43' pid=2893289 parent=2854029 started>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7da5db0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.14325s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.14333s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.14335s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.14339s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.14341s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.14343s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.14344s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_629] | 1 | True | 600.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_629' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_629', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-23' pid=2894196 parent=2854326 started>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a4ce920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7112s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7117s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7119s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7123s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7125s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7126s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7128s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1429] | 1 | True | 600.10 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1429' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1429', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-35' pid=2894286 parent=2853913 started>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d57f700 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4088s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12831s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12840s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12845s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12847s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12848s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12850s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12852s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_112] | 1 | True | 0.11 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_112' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_112', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-26' pid=2894569 parent=2854130 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c43ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1646s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6634023677566856 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25891189 bytes MEM: Free's : 26 free's of 25891189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6634023677566856 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_35] | 1 | True | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_35' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_35', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-51' pid=2894701 parent=2854331 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc370340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11801s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5712166223210411 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30258349 bytes MEM: Free's : 26 free's of 30258349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5712166223210411 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_55] | 1 | True | 600.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_55' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_55', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-63' pid=2895943 parent=2854331 started>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc385520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6137s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6142s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6143s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6148s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6149s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6150s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6151s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_50] | 1 | True | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_50' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_50', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=2896325 parent=2854468 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fb5380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20467264 bytes MEM: Free's : 26 free's of 20467264 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (35, 83, 83) got (35, 80, 80) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_235] | 1 | True | 600.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_235' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_235', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-36' pid=2896461 parent=2854095 started>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529abc63f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.15914s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.15921s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.15926s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.15927s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.15928s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.15929s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.15930s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1009] | 1 | True | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1009' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1009', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-52' pid=2897153 parent=2853921 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436333c660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6009501134787559 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23848720 bytes MEM: Free's : 26 free's of 23848720 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6009501134787559 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_601] | 1 | True | 600.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_601' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_601', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-27' pid=2897613 parent=2854291 started>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e0ccb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.14100s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.14118s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.14120s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.14130s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.14132s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.14135s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.14137s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_456] | 1 | True | 600.10 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_456' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_456', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-33' pid=2897746 parent=2854164 started>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e86b8c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5837s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5845s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5853s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5855s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5856s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5859s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5861s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_97] | 1 | True | 600.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_97' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_97', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-58' pid=2898159 parent=2853921 started>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631ce0b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.8430s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.8436s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.8438s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.8443s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.8444s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.8447s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.8448s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1069] | 1 | True | 600.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1069' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1069', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-42' pid=2898419 parent=2854565 started>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090de9c90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5099s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5104s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5105s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5109s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5111s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5113s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5114s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_401] | 1 | True | 0.16 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_401' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_401', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-24' pid=2898819 parent=2853910 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb201ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6020000943050552 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70162253 bytes MEM: Free's : 26 free's of 70162253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6020000943050552 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_701] | 1 | True | 600.10 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_701' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_701', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-37' pid=2899167 parent=2853959 started>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a54ba30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.19796s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.19804s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.19808s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.19809s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.19810s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.19811s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.19812s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_205] | 1 | True | 600.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_205' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_205', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-55' pid=2901766 parent=2854468 started>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ba9e60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.13635s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.13641s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.13643s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.13648s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.13649s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.13651s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.13653s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_969] | 1 | True | 600.10 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_969' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_969', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-49' pid=2902163 parent=2853910 started>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb13eeb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4283s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4288s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4290s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4294s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4296s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4298s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4300s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1127] | 1 | True | 600.10 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1127' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1127', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-32' pid=2903382 parent=2854366 started>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97ae6c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6071s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6076s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6077s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6081s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6082s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6084s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6085s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_317] | 1 | True | 0.07 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_317' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_317', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-32' pid=2903911 parent=2854130 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c4d2a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14990949 bytes MEM: Free's : 26 free's of 14990949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 24, 34, 36) got (4, 24, 32, 32) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_427] | 1 | True | 0.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_427' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_427', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=2904326 parent=2854130 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237db5900 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1257s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.602295834152375 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20247421 bytes MEM: Free's : 26 free's of 20247421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.602295834152375 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_490] | 1 | True | 600.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_490' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_490', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-48' pid=2905391 parent=2853924 started>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3dd9a70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5400s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5407s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5409s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5413s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5414s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5416s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5418s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_243] | 1 | True | 600.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_243' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_243', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-47' pid=2905743 parent=2854130 started>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c70af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3365s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3369s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3370s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3374s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3375s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3377s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3379s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_406] | 1 | True | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_406' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_406', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-61' pid=2906779 parent=2853993 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00934130 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 206868373 bytes MEM: Free's : 26 free's of 206868373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 288, 89, 87) got (4, 288, 86, 86) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_62] | 1 | True | 0.12 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_62' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_62', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-86' pid=2907219 parent=2854890 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c68280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48960725 bytes MEM: Free's : 26 free's of 48960725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-86: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (4, 8, 110, 110) got (4, 8, 105, 105) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1438] | 1 | True | 600.10 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1438' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1438', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-87' pid=2907284 parent=2854890 started>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b81210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5081s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5087s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5088s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5091s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5092s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5094s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5095s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_416] | 1 | True | 600.10 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_416' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_416', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-73' pid=2907442 parent=2853907 started>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4314010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.13415s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.13422s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.13424s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.13429s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.13430s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.13432s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.13434s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_119] | 1 | True | 600.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_119' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_119', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-73' pid=2907728 parent=2853993 started>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00860930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1202s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1204s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4729s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4733s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4734s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4738s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4739s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4740s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4742s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_51] | 1 | True | 600.11 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_51' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_51', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-6' pid=2908419 parent=2853904 started>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fcab70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.244s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.8995s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.8999s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.9004s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.9005s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.9006s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.9008s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.9010s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_203] | 1 | True | 600.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_203' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_203', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-15' pid=2908746 parent=2853916 started>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008e3750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12559s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12565s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12566s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12570s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12571s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12573s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12574s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_481] | 1 | True | 600.02 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_481' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_481', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-18' pid=2909233 parent=2854694 started>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e78b960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5265s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5270s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5271s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5275s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5276s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5278s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5279s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_175] | 1 | True | 600.10 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_175' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_175', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-37' pid=2911192 parent=2853913 started>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d49af50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6961s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6966s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6967s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6973s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6975s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6977s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6978s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_860] | 1 | True | 600.10 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_860' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_860', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-47' pid=2911503 parent=2854728 started>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7737aba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6906s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6914s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6915s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6920s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6922s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6924s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6925s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1057] | 1 | True | 600.11 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1057' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1057', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-30' pid=2911632 parent=2854463 started>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884eb610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.14070s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.14082s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.14091s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.14092s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.14094s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.14096s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.14097s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1105] | 1 | True | 600.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1105' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1105', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-26' pid=2911745 parent=2853901 started>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da716e90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6236s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6241s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6242s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6246s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6247s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6249s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6250s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_99] | 1 | True | 600.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_99' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_99', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-71' pid=2913054 parent=2854331 started>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2ad290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6336s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6340s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6341s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6345s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6346s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6348s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6349s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_833] | 1 | True | 600.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_833' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_833', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-37' pid=2913143 parent=2854095 started>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529b169860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12344s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12350s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12356s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12357s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12359s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12360s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12361s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1033] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1033' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1033', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-59' pid=2913427 parent=2854029 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece821dc90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5676361099454785 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23800525 bytes MEM: Free's : 26 free's of 23800525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5676361099454785 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1029] | 1 | True | 0.09 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1029' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1029', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-34' pid=2913646 parent=2854164 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e784bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5342644169310193 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25363949 bytes MEM: Free's : 26 free's of 25363949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5342644169310193 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_171] | 1 | True | 600.07 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_171' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_171', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-35' pid=2913712 parent=2854164 started>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e788730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3934s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3938s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3939s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3946s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3947s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3949s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3951s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_338] | 1 | True | 600.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_338' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_338', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-66' pid=2914808 parent=2853921 started>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630ecae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3252s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3270s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3272s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3276s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3277s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3279s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3280s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_63] | 1 | True | 600.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_63' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_63', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-31' pid=2914938 parent=2854291 started>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e151f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.16740s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.16750s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.16758s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.16759s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.16760s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.16762s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.16764s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1089] | 1 | True | 600.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1089' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1089', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-54' pid=2915318 parent=2854565 started>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d81200 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.11430s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.11435s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.11436s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.11441s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.11442s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.11444s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.11445s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1061] | 1 | True | 600.10 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1061' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1061', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-53' pid=2917340 parent=2853959 started>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a941b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5867s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.28979s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.28984s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.28988s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.28989s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.28990s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.28992s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.28993s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_95] | 1 | True | 600.10 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_95' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_95', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-57' pid=2918675 parent=2853910 started>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb233d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.13182s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.13198s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.13200s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.13208s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.13209s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.13211s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.13213s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_69] | 1 | True | 600.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_69' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_69', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-107' pid=2919144 parent=2854029 started>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81f6a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6327s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6348s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6350s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6354s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6355s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6357s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6359s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_159] | 1 | True | 600.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_159' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_159', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-47' pid=2919534 parent=2854326 started>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e5ecc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4951s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4956s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4957s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4961s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4962s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4964s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4965s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_606] | 1 | True | 0.16 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_606' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_606', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-63' pid=2919796 parent=2854468 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48baf560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6484343223138356 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25741465 bytes MEM: Free's : 26 free's of 25741465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6484343223138356 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_394] | 1 | True | 600.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_394' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_394', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-53' pid=2920553 parent=2853924 started>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40a7570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1967s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.10203s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.10223s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.10228s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.10229s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.10230s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.10231s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.10232s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_581] | 1 | True | 600.06 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_581' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_581', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-77' pid=2921342 parent=2854468 started>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fc13d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.19940s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.19949s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.19955s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.19956s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.19957s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.19959s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.19960s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_665] | 1 | True | 600.09 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_665' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_665', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-41' pid=2921801 parent=2854366 started>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9ac9ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6421s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6424s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6426s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6429s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6431s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6433s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6434s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_195] | 1 | True | 600.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_195' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_195', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-64' pid=2922373 parent=2854130 started>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c323798f5f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6377s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6382s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6384s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6388s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6390s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6391s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6393s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1045] | 1 | True | 600.10 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1045' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1045', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-75' pid=2923017 parent=2853907 started>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4736c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6563s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6570s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6570s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6574s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6575s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6577s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6578s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_549] | 1 | True | 600.10 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_549' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_549', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-101' pid=2923082 parent=2854890 started>.exitcode test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c8fe50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1241s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1243s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.8727s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.8731s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.8732s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.8736s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.8737s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.8739s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.8740s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_466] | 1 | True | 600.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_466' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_466', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-97' pid=2924241 parent=2853993 started>.exitcode test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0096ec70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6930s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6933s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6937s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6938s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6939s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6941s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6943s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_91] | 1 | True | 600.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_91' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_91', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-18' pid=2925479 parent=2853916 started>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8007f8410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3414s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3419s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3423s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3424s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3425s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3426s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3428s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_31] | 1 | True | 0.07 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_31' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_31', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-20' pid=2925722 parent=2854694 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6a5ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6134771794917558 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20419008 bytes MEM: Free's : 26 free's of 20419008 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6134771794917558 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_836] | 1 | True | 600.10 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_836' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_836', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-39' pid=2925947 parent=2853913 started>.exitcode test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d49ebb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5076s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5082s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5083s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5087s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5087s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5089s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5090s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_279] | 1 | True | 600.10 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_279' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_279', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-31' pid=2926077 parent=2854463 started>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d388406790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6512s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6533s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6534s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6538s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6539s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6540s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6542s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_271] | 1 | True | 600.09 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_271' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_271', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-54' pid=2926842 parent=2854728 started>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda776883c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7518s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7527s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7534s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7535s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7537s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7538s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7540s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_875] | 1 | True | 600.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_875' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_875', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-41' pid=2928223 parent=2853901 started>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da388af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.5188s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.5206s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.5208s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.5212s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.5213s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.5215s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.5217s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_391] | 1 | True | 600.10 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_391' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_391', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-40' pid=2928377 parent=2854164 started>.exitcode test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e4ad240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.6352s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.6357s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.6358s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.6363s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.6364s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.6366s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.6367s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1093] | 1 | True | 600.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1093' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1093', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-67' pid=2928686 parent=2853921 started>.exitcode test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631d9de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.9179s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.9184s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.9185s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.9191s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.9192s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.9194s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.9196s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_87] | 1 | True | 600.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_87' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_87', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-33' pid=2928882 parent=2854291 started>.exitcode test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164f05a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.9326s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.9340s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.9348s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.9349s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.9350s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.9352s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.9353s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1049] | 1 | True | 600.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1049' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1049', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-23' pid=2928947 parent=2853904 started>.exitcode test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6ff34c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12237s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12243s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12244s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12249s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12250s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12252s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12253s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_135] | 1 | True | 600.06 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_135' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_135', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-56' pid=2929036 parent=2854565 started>.exitcode test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d8ac80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12733s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12740s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12742s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12747s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12748s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12750s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12751s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1133] | 1 | True | 600.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1133' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1133', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-85' pid=2929433 parent=2854331 started>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3afef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1202s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1204s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.12622s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.12628s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.12629s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.12633s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.12634s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.12636s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.12637s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_479] | 1 | True | 600.10 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_479' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_479', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-55' pid=2929525 parent=2853959 started>.exitcode test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a8620a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1185s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3550s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3554s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3556s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3559s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3560s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3562s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3563s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_59] | 1 | True | 600.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_59' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_59', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-62' pid=2930251 parent=2853910 started>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb155610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.7132s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.7146s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.7156s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.7157s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.7158s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.7161s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.7163s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_11] | 1 | True | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_11' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_11', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-49' pid=2930535 parent=2854095 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afbd7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6286432285829728 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59839992 bytes MEM: Free's : 26 free's of 59839992 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6286432285829728 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_938] | 1 | True | 0.13 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_938' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_938', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-114' pid=2930976 parent=2854029 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81fb210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5791737485272415 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42571085 bytes MEM: Free's : 26 free's of 42571085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-114: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5791737485272415 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_103] | 1 | True | 600.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_103' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_103', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-115' pid=2931235 parent=2854029 started>.exitcode test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81185c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3731s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3735s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3736s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3740s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3741s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3743s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3745s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_435] | 1 | True | 600.03 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_435' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_435', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-57' pid=2931625 parent=2854095 started>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aee5bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4492s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4496s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4497s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4501s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4502s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4503s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4505s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_934] | 1 | True | 0.09 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_934' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_934', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-50' pid=2932440 parent=2854694 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6da780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6297515640393386 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28683269 bytes MEM: Free's : 26 free's of 28683269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6297515640393386 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_359] | 1 | True | 600.11 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_359' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_359', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-55' pid=2932960 parent=2853924 started>.exitcode test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40b1680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.3889s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.3895s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.3896s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.3900s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.3902s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.3904s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.3905s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_300] | 1 | True | 0.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_300' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_300', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-52' pid=2933090 parent=2854326 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a254e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5647422407429994 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30257325 bytes MEM: Free's : 26 free's of 30257325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5647422407429994 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_46] | 1 | True | 0.33 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_46' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_46', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-54' pid=2933268 parent=2854326 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a260f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 117979925 bytes MEM: Free's : 26 free's of 117979925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (2, 184, 111, 111) got (2, 184, 110, 110) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1005] | 1 | True | 0.08 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_1005' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_1005', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-58' pid=2933333 parent=2854694 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6eb9d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5756844219348445 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19064240 bytes MEM: Free's : 26 free's of 19064240 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5756844219348445 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_67] | 1 | True | 600.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_67' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_67', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-68' pid=2934943 parent=2854326 started>.exitcode test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a281b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1872s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.20158s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.20167s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.20173s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.20175s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.20176s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.20177s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.20178s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_621] | 1 | True | 600.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_621' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_621', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-88' pid=2935121 parent=2854468 started>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ee61b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.11238s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.11244s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.11248s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.11249s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.11249s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.11250s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.11251s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_58] | 1 | True | 0.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_58' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_58', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-69' pid=2935253 parent=2854694 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7f04f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 117979925 bytes MEM: Free's : 26 free's of 117979925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (2, 184, 114, 114) got (2, 184, 110, 110) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_27] | 1 | True | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_27' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_27', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-45' pid=2935868 parent=2854366 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9bb3d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.189s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.570932430760873 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75489765 bytes MEM: Free's : 26 free's of 75489765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.570932430760873 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_42] | 1 | True | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_42' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_42', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-79' pid=2936072 parent=2853907 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46feed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47916069 bytes MEM: Free's : 26 free's of 47916069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 174, in perform_tidl_unit_oneprocess max_nmse = tidl_unit_dataset([results_list])['max_nmse'] File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/datasets/tidl_unit_dataset.py", line 132, in __call__ assert expected_output.shape == output.shape, f" Shape mismatch! Expected {expected_output.shape} got {output.shape}" AssertionError: Shape mismatch! Expected (2, 184, 65, 65) got (2, 184, 64, 64) | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_139] | 1 | True | 600.10 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_139' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_139', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-33' pid=2937321 parent=2854463 started>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d38840c110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4863s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4867s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4868s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4872s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4873s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4875s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4876s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_966] | 1 | True | 600.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Convolution_966' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Convolution_966', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Convolution' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: None E assert None == 0 E + where None = <Process name='Process-42' pid=2937609 parent=2853901 started>.exitcode test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da64c650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 0.4566s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.4571s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.4572s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.4575s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.4576s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.4577s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.4579s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_202] | 1 | True | 1.05 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6f807d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8792s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014829636526430583 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 772.36 Core Time (ms) : 770.75 TIDL Subgraphs Processing Time (ms) : 770.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39071307 bytes MEM: Free's : 26 free's of 39071307 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_985] | 0 | - | 0.31 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc007945f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.40 Core Time (ms) : 1.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_415] | 1 | True | 0.75 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80f5ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.43481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.43536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.43559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.43596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.43628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.43653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.43677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.43705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.43727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.43748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.43777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.43802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.43835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.43856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.43883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.43911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.43936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.43957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.43982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.44003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.44028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.44054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.44074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.44103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.44124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.44144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.44169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.44198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.44221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.44247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.44271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.44299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.44302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.44304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018384625742010155 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 353.60 Core Time (ms) : 351.91 TIDL Subgraphs Processing Time (ms) : 351.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34728821 bytes MEM: Free's : 26 free's of 34728821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_49] | 1 | True | 0.31 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f461d790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2106s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00036954354093256974 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.40 Core Time (ms) : 89.38 TIDL Subgraphs Processing Time (ms) : 89.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40778741 bytes MEM: Free's : 26 free's of 40778741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_647] | 1 | True | 2.53 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3bb06d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1852s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001608178168316654 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2106.57 Core Time (ms) : 2090.05 TIDL Subgraphs Processing Time (ms) : 2089.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 142756005 bytes MEM: Free's : 26 free's of 142756005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1248] | 1 | True | 0.46 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae80078cc20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23398s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014797074118332547 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 104.96 Core Time (ms) : 104.64 TIDL Subgraphs Processing Time (ms) : 104.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18951997 bytes MEM: Free's : 26 free's of 18951997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1412] | 0 | - | 0.34 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436311d760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.45 Core Time (ms) : 2.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_397] | 0 | - | 0.22 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164d94220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_789] | 1 | True | 0.85 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af19c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017485492666301667 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 391.77 Core Time (ms) : 379.59 TIDL Subgraphs Processing Time (ms) : 379.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68085341 bytes MEM: Free's : 26 free's of 68085341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1452] | 0 | - | 0.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a33f0a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.24 Core Time (ms) : 2.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_536] | 1 | True | 0.34 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e7ee2e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5788s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001538881408974118 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.22 Core Time (ms) : 54.79 TIDL Subgraphs Processing Time (ms) : 54.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34766293 bytes MEM: Free's : 26 free's of 34766293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_559] | 1 | True | 1.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090cdd1f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001670498987824564 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 769.42 Core Time (ms) : 758.60 TIDL Subgraphs Processing Time (ms) : 758.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 199562241 bytes MEM: Free's : 26 free's of 199562241 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_994] | 0 | - | 0.41 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc314180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 90.54 Core Time (ms) : 90.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_238] | 1 | True | 1.24 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e72b850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015137962394554978 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 865.61 Core Time (ms) : 863.77 TIDL Subgraphs Processing Time (ms) : 863.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42579809 bytes MEM: Free's : 26 free's of 42579809 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1135] | 1 | True | 10.34 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68683fef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3038s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002151418132624566 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8881.06 Core Time (ms) : 8828.45 TIDL Subgraphs Processing Time (ms) : 8821.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1140898677 bytes MEM: Free's : 26 free's of 1140898677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_383] | 0 | - | 0.14 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda775e2060 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_733] | 1 | True | 0.38 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237bccc50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.716396506027159e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 135.01 Core Time (ms) : 134.65 TIDL Subgraphs Processing Time (ms) : 134.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17745749 bytes MEM: Free's : 26 free's of 17745749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_929] | 1 | True | 3.43 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48a6a5a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.137s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5968s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015965998243350094 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2760.90 Core Time (ms) : 2750.96 TIDL Subgraphs Processing Time (ms) : 2750.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 189398597 bytes MEM: Free's : 26 free's of 189398597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_480] | 0 | - | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb0a4400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.940083363971682e-19 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.32 Core Time (ms) : 9.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_978] | 1 | True | 0.46 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6a3f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1645s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015144928180505198 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 87.27 Core Time (ms) : 86.02 TIDL Subgraphs Processing Time (ms) : 85.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29624669 bytes MEM: Free's : 26 free's of 29624669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1415] | 0 | - | 0.15 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a8a1620 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.37 Core Time (ms) : 20.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_142] | 1 | True | 0.24 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda775e64a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16806s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00477957107811431 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.66 Core Time (ms) : 20.51 TIDL Subgraphs Processing Time (ms) : 20.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19648209 bytes MEM: Free's : 26 free's of 19648209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_882] | 1 | True | 5.31 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a426520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017016179401549203 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4261.39 Core Time (ms) : 4223.53 TIDL Subgraphs Processing Time (ms) : 4222.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 627424053 bytes MEM: Free's : 26 free's of 627424053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_999] | 1 | True | 1.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e7eb10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017914699676884418 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 472.71 Core Time (ms) : 448.09 TIDL Subgraphs Processing Time (ms) : 445.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 249112630 bytes MEM: Free's : 26 free's of 249112630 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_269] | 1 | True | 1.97 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb192e60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001658216488583969 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1514.09 Core Time (ms) : 1511.32 TIDL Subgraphs Processing Time (ms) : 1511.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64336773 bytes MEM: Free's : 26 free's of 64336773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1137] | 1 | True | 0.92 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc004eacd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.137s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001507908148668068 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 479.96 Core Time (ms) : 478.25 TIDL Subgraphs Processing Time (ms) : 478.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41241981 bytes MEM: Free's : 26 free's of 41241981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_688] | 1 | True | 0.62 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f41a67b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1642s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015005439864691986 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 376.14 Core Time (ms) : 374.82 TIDL Subgraphs Processing Time (ms) : 374.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35781633 bytes MEM: Free's : 26 free's of 35781633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_77] | 1 | True | 3.35 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1b0bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016895740864343123 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2152.22 Core Time (ms) : 2111.76 TIDL Subgraphs Processing Time (ms) : 2109.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 779625781 bytes MEM: Free's : 26 free's of 779625781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_230] | 1 | True | 0.58 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363124650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.143s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2476s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014487830077967355 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 334.78 Core Time (ms) : 333.93 TIDL Subgraphs Processing Time (ms) : 333.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30173733 bytes MEM: Free's : 26 free's of 30173733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1162] | 0 | - | 0.18 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e709ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.597997439641917e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.33 Core Time (ms) : 6.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_572] | 1 | True | 0.67 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda776d4090 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.190s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015140062660851824 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 243.64 Core Time (ms) : 240.86 TIDL Subgraphs Processing Time (ms) : 240.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65326769 bytes MEM: Free's : 26 free's of 65326769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_685] | 1 | True | 1.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237964e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016040753051262298 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 948.94 Core Time (ms) : 942.98 TIDL Subgraphs Processing Time (ms) : 942.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73975025 bytes MEM: Free's : 26 free's of 73975025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_940] | 1 | True | 0.41 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2cf980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000171534802131444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 108.47 Core Time (ms) : 106.46 TIDL Subgraphs Processing Time (ms) : 106.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38570077 bytes MEM: Free's : 26 free's of 38570077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1179] | 1 | True | 0.37 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da5c1050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.287050309337249e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 164.17 Core Time (ms) : 163.79 TIDL Subgraphs Processing Time (ms) : 163.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21572049 bytes MEM: Free's : 26 free's of 21572049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_809] | 1 | True | 0.29 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e7f3340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001648830646288351 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.54 Core Time (ms) : 27.97 TIDL Subgraphs Processing Time (ms) : 27.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35082709 bytes MEM: Free's : 26 free's of 35082709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_742] | 0 | - | 0.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80f8380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7270269122366255e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.28 Core Time (ms) : 1.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_462] | 1 | True | 0.16 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc1eb0f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014602455389368151 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.94 Core Time (ms) : 24.78 TIDL Subgraphs Processing Time (ms) : 24.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18565005 bytes MEM: Free's : 26 free's of 18565005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1035] | 1 | True | 0.25 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e7f8890 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00019244269633704266 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.15 Core Time (ms) : 19.77 TIDL Subgraphs Processing Time (ms) : 19.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23892557 bytes MEM: Free's : 26 free's of 23892557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_196] | 0 | - | 0.08 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da5c61a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_680] | 1 | True | 0.22 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae352f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.780626637880138e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.48 Core Time (ms) : 15.32 TIDL Subgraphs Processing Time (ms) : 15.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15186673 bytes MEM: Free's : 26 free's of 15186673 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_845] | 0 | - | 0.15 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8014c30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.83 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_682] | 0 | - | 0.37 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d2643e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7056643120566295e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 64.21 Core Time (ms) : 64.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_770] | 0 | - | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8005212c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2545545017337449e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.57 Core Time (ms) : 22.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_155] | 1 | True | 1.18 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da22c690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016967948737089296 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 908.34 Core Time (ms) : 900.90 TIDL Subgraphs Processing Time (ms) : 900.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 87753037 bytes MEM: Free's : 26 free's of 87753037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1319] | 1 | True | 0.55 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436303b300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017939762336043654 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 295.32 Core Time (ms) : 288.68 TIDL Subgraphs Processing Time (ms) : 288.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 91123437 bytes MEM: Free's : 26 free's of 91123437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_891] | 1 | True | 1.08 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f25b5640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015522616129615404 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 823.76 Core Time (ms) : 817.22 TIDL Subgraphs Processing Time (ms) : 817.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 105409189 bytes MEM: Free's : 26 free's of 105409189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1159] | 1 | True | 0.32 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc1eb800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1955s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001494314169333721 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 108.15 Core Time (ms) : 107.58 TIDL Subgraphs Processing Time (ms) : 107.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19514557 bytes MEM: Free's : 26 free's of 19514557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_635] | 1 | True | 0.29 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8101780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001405548318147564 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.57 Core Time (ms) : 40.77 TIDL Subgraphs Processing Time (ms) : 40.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25969749 bytes MEM: Free's : 26 free's of 25969749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_642] | 0 | - | 0.12 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77698a80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1324] | 1 | True | 0.21 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae37310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001365992695811663 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.65 Core Time (ms) : 6.49 TIDL Subgraphs Processing Time (ms) : 6.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17892625 bytes MEM: Free's : 26 free's of 17892625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_26] | 1 | True | 0.34 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e70e830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1089s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00010587867932923718 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.24 Core Time (ms) : 34.97 TIDL Subgraphs Processing Time (ms) : 34.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39157933 bytes MEM: Free's : 26 free's of 39157933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1189] | 1 | True | 0.26 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77289640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015311375273143003 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.34 Core Time (ms) : 53.03 TIDL Subgraphs Processing Time (ms) : 52.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23476137 bytes MEM: Free's : 26 free's of 23476137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_909] | 1 | True | 0.35 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00884ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6001s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00020771158503194852 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 117.22 Core Time (ms) : 114.93 TIDL Subgraphs Processing Time (ms) : 114.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55565917 bytes MEM: Free's : 26 free's of 55565917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1385] | 0 | - | 0.12 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7585f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_720] | 1 | True | 0.51 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090ce7fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8814s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015197138441834393 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 329.43 Core Time (ms) : 327.96 TIDL Subgraphs Processing Time (ms) : 327.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33318517 bytes MEM: Free's : 26 free's of 33318517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1121] | 1 | True | 0.15 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae380d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.225s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.799185636495943e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.71 Core Time (ms) : 6.66 TIDL Subgraphs Processing Time (ms) : 6.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13175413 bytes MEM: Free's : 26 free's of 13175413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_400] | 1 | True | 0.35 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d5436f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8910s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002130622881749318 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 75.58 Core Time (ms) : 71.47 TIDL Subgraphs Processing Time (ms) : 71.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 80548389 bytes MEM: Free's : 26 free's of 80548389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1149] | 1 | True | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81713a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001406223596379814 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.83 Core Time (ms) : 53.62 TIDL Subgraphs Processing Time (ms) : 53.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18282235 bytes MEM: Free's : 26 free's of 18282235 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_724] | 1 | True | 0.28 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc1ebed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014316559791509764 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 125.85 Core Time (ms) : 125.63 TIDL Subgraphs Processing Time (ms) : 125.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20051389 bytes MEM: Free's : 26 free's of 20051389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_111] | 1 | True | 0.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e83ed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014954447194635558 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 73.33 Core Time (ms) : 72.37 TIDL Subgraphs Processing Time (ms) : 72.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30069685 bytes MEM: Free's : 26 free's of 30069685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_873] | 0 | - | 0.08 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e7165f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.9214382798281335e-16 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.81 Core Time (ms) : 0.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_221] | 1 | True | 0.25 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af3d740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4080s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4082s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001498526742850502 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 100.12 Core Time (ms) : 99.80 TIDL Subgraphs Processing Time (ms) : 99.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20356165 bytes MEM: Free's : 26 free's of 20356165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1295] | 1 | True | 0.21 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436303a240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00019588953423576905 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.57 Core Time (ms) : 20.86 TIDL Subgraphs Processing Time (ms) : 19.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29344709 bytes MEM: Free's : 26 free's of 29344709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_153] | 1 | True | 0.66 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8016450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001705433996781223 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 388.58 Core Time (ms) : 381.36 TIDL Subgraphs Processing Time (ms) : 381.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 91112949 bytes MEM: Free's : 26 free's of 91112949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_457] | 0 | - | 0.09 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e92c100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.89 Core Time (ms) : 0.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_749] | 1 | True | 1.49 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc005aba80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1726s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1728s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016143397725319343 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1315.18 Core Time (ms) : 1311.53 TIDL Subgraphs Processing Time (ms) : 1311.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76581013 bytes MEM: Free's : 26 free's of 76581013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_895] | 0 | - | 0.04 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbdb31e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.309459823266876e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.55 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_283] | 1 | True | 2.09 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e476b10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0007030563829470622 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1897.19 Core Time (ms) : 1892.94 TIDL Subgraphs Processing Time (ms) : 1892.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96445493 bytes MEM: Free's : 26 free's of 96445493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1119] | 1 | True | 0.92 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d54e0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002135209982905895 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 750.58 Core Time (ms) : 747.06 TIDL Subgraphs Processing Time (ms) : 746.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70451240 bytes MEM: Free's : 26 free's of 70451240 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1338] | 1 | True | 0.35 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2dd780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015745103334201127 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 140.98 Core Time (ms) : 139.70 TIDL Subgraphs Processing Time (ms) : 139.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29742069 bytes MEM: Free's : 26 free's of 29742069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_241] | 1 | True | 8.59 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164baa140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016486085844243003 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7825.60 Core Time (ms) : 7792.45 TIDL Subgraphs Processing Time (ms) : 7790.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 577751373 bytes MEM: Free's : 26 free's of 577751373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_485] | 1 | True | 0.21 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af262e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015507457778066484 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 85.31 Core Time (ms) : 84.85 TIDL Subgraphs Processing Time (ms) : 84.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24228477 bytes MEM: Free's : 26 free's of 24228477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1042] | 0 | - | 0.11 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436303cce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.651495641631785e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.83 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1477] | 1 | True | 0.23 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f508ec6a020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001523971546772803 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.63 Core Time (ms) : 53.43 TIDL Subgraphs Processing Time (ms) : 53.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30731605 bytes MEM: Free's : 26 free's of 30731605 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_389] | 0 | - | 0.07 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237bd6a70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.36 Core Time (ms) : 9.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1032] | 1 | True | 0.15 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436303e560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00010810908795531503 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.87 Core Time (ms) : 7.73 TIDL Subgraphs Processing Time (ms) : 7.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20438245 bytes MEM: Free's : 26 free's of 20438245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_432] | 0 | - | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237e38200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.97 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1214] | 0 | - | 0.08 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae3ec00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.946147695107953e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.46 Core Time (ms) : 15.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1116] | 1 | True | 2.74 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237965520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016390660317792304 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2452.35 Core Time (ms) : 2439.46 TIDL Subgraphs Processing Time (ms) : 2439.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 265889385 bytes MEM: Free's : 26 free's of 265889385 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_297] | 1 | True | 0.26 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436312a980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017724484852786737 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.08 Core Time (ms) : 55.59 TIDL Subgraphs Processing Time (ms) : 55.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74073437 bytes MEM: Free's : 26 free's of 74073437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_237] | 1 | True | 1.22 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aab8850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001499952831519763 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 984.45 Core Time (ms) : 975.85 TIDL Subgraphs Processing Time (ms) : 975.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 123383249 bytes MEM: Free's : 26 free's of 123383249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1155] | 1 | True | 1.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2e2680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3031s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001540270762935239 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 878.16 Core Time (ms) : 872.23 TIDL Subgraphs Processing Time (ms) : 872.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 79925681 bytes MEM: Free's : 26 free's of 79925681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_546] | 0 | - | 0.10 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f453d5e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.2803537955609495e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.78 Core Time (ms) : 0.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_533] | 1 | True | 0.24 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6af150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015794055663054707 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 72.70 Core Time (ms) : 71.55 TIDL Subgraphs Processing Time (ms) : 71.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48188501 bytes MEM: Free's : 26 free's of 48188501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1185] | 1 | True | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f41a67a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9073s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001497894670622113 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 72.37 Core Time (ms) : 72.16 TIDL Subgraphs Processing Time (ms) : 72.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21590717 bytes MEM: Free's : 26 free's of 21590717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_630] | 0 | - | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8109120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.450545417261858e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_566] | 0 | - | 0.07 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb191a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.3829405710178525e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_687] | 1 | True | 0.83 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631335a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015409868369591507 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 675.25 Core Time (ms) : 672.14 TIDL Subgraphs Processing Time (ms) : 672.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69585789 bytes MEM: Free's : 26 free's of 69585789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_868] | 1 | True | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8103f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015267859833484833 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.95 Core Time (ms) : 27.38 TIDL Subgraphs Processing Time (ms) : 27.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27428437 bytes MEM: Free's : 26 free's of 27428437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_220] | 0 | - | 0.06 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb198390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.90 Core Time (ms) : 11.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_798] | 1 | True | 0.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f462a2c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1800s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001518200025757188 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.13 Core Time (ms) : 63.67 TIDL Subgraphs Processing Time (ms) : 63.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42456661 bytes MEM: Free's : 26 free's of 42456661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1288] | 0 | - | 0.09 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da5c7580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_960] | 1 | True | 0.14 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece801b910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017206274528842362 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.20 Core Time (ms) : 38.51 TIDL Subgraphs Processing Time (ms) : 38.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25418453 bytes MEM: Free's : 26 free's of 25418453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1342] | 1 | True | 0.12 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da5cb4d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015567396185446223 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.94 Core Time (ms) : 16.74 TIDL Subgraphs Processing Time (ms) : 15.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18191937 bytes MEM: Free's : 26 free's of 18191937 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_522] | 0 | - | 0.16 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f462ed50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.646065745647084e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.57 Core Time (ms) : 21.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1426] | 1 | True | 0.18 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6b4fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017161137171273772 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.92 Core Time (ms) : 29.01 TIDL Subgraphs Processing Time (ms) : 28.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29638461 bytes MEM: Free's : 26 free's of 29638461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1249] | 1 | True | 0.24 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece810e3e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015778056981869011 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 131.31 Core Time (ms) : 130.38 TIDL Subgraphs Processing Time (ms) : 130.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47850485 bytes MEM: Free's : 26 free's of 47850485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1175] | 1 | True | 0.44 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4632b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014824595945338474 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 307.97 Core Time (ms) : 305.66 TIDL Subgraphs Processing Time (ms) : 305.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43049133 bytes MEM: Free's : 26 free's of 43049133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1230] | 0 | - | 0.05 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da5cc7f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_788] | 0 | - | 0.05 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6e8db0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_532] | 1 | True | 0.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece818ad60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1630s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001666808737358238 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.85 Core Time (ms) : 2.69 TIDL Subgraphs Processing Time (ms) : 2.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15531525 bytes MEM: Free's : 26 free's of 15531525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1466] | 0 | - | 0.05 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8021f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1236] | 1 | True | 0.98 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614362e4b5c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015624780848617984 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 818.96 Core Time (ms) : 815.88 TIDL Subgraphs Processing Time (ms) : 815.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60701173 bytes MEM: Free's : 26 free's of 60701173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1184] | 1 | True | 0.35 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00795b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3987s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001525574345900152 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 223.66 Core Time (ms) : 222.50 TIDL Subgraphs Processing Time (ms) : 222.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33760253 bytes MEM: Free's : 26 free's of 33760253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_528] | 1 | True | 0.16 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc1f3aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001392783017004486 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.69 Core Time (ms) : 8.48 TIDL Subgraphs Processing Time (ms) : 8.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21758593 bytes MEM: Free's : 26 free's of 21758593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_782] | 0 | - | 0.06 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f462f190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2274725673533315e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.15 Core Time (ms) : 1.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_302] | 1 | True | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af2b830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.8136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018738087443690116 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.86 Core Time (ms) : 26.95 TIDL Subgraphs Processing Time (ms) : 26.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37857733 bytes MEM: Free's : 26 free's of 37857733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1465] | 1 | True | 0.13 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45484a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.148s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001493451555308347 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.87 Core Time (ms) : 12.58 TIDL Subgraphs Processing Time (ms) : 12.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17974705 bytes MEM: Free's : 26 free's of 17974705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_673] | 1 | True | 0.95 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7e01ac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015809654206673477 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 791.42 Core Time (ms) : 787.31 TIDL Subgraphs Processing Time (ms) : 787.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 95502353 bytes MEM: Free's : 26 free's of 95502353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1166] | 0 | - | 0.07 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4639820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4957579614344e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.78 Core Time (ms) : 0.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1218] | 0 | - | 0.07 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aab27e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.105720853000754e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.56 Core Time (ms) : 4.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_349] | 1 | True | 0.36 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e01530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.681690462006395e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 161.10 Core Time (ms) : 151.59 TIDL Subgraphs Processing Time (ms) : 151.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 98320901 bytes MEM: Free's : 26 free's of 98320901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_133] | 1 | True | 0.15 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc007a20d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011358372221895983 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.67 Core Time (ms) : 8.53 TIDL Subgraphs Processing Time (ms) : 8.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14129069 bytes MEM: Free's : 26 free's of 14129069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1178] | 0 | - | 0.08 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae4b110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.82 Core Time (ms) : 14.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_772] | 0 | - | 0.02 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af9a540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_904] | 0 | - | 0.17 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aabf220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.19 Core Time (ms) : 16.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1395] | 0 | - | 0.24 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689d2f150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.37 Core Time (ms) : 16.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1353] | 1 | True | 1.55 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e4b6480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0037898515485034257 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1278.63 Core Time (ms) : 1266.51 TIDL Subgraphs Processing Time (ms) : 1266.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 177411313 bytes MEM: Free's : 26 free's of 177411313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_746] | 0 | - | 0.08 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f467a180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1145] | 1 | True | 0.19 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e11c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015930290166908567 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.72 Core Time (ms) : 37.43 TIDL Subgraphs Processing Time (ms) : 37.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19746160 bytes MEM: Free's : 26 free's of 19746160 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1164] | 1 | True | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af4c4c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014107523562132722 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 57.86 Core Time (ms) : 57.58 TIDL Subgraphs Processing Time (ms) : 57.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19360045 bytes MEM: Free's : 26 free's of 19360045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1177] | 1 | True | 0.28 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4681d80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015575606990452897 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 159.74 Core Time (ms) : 158.31 TIDL Subgraphs Processing Time (ms) : 158.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52252789 bytes MEM: Free's : 26 free's of 52252789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1056] | 1 | True | 0.09 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a0cdc50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4080s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0078431940873398 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.46 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 1.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14663733 bytes MEM: Free's : 26 free's of 14663733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_716] | 1 | True | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008d7200 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015484387701856717 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 152.75 Core Time (ms) : 152.21 TIDL Subgraphs Processing Time (ms) : 152.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31556909 bytes MEM: Free's : 26 free's of 31556909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_679] | 1 | True | 1.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48eead30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001572392657945135 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1055.26 Core Time (ms) : 1051.69 TIDL Subgraphs Processing Time (ms) : 1051.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65163325 bytes MEM: Free's : 26 free's of 65163325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_690] | 0 | - | 0.07 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae49cf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.886247865184033e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.19 Core Time (ms) : 1.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_538] | 0 | - | 0.06 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a0cd6a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.5783944029376825e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.01 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_336] | 1 | True | 2.68 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1b8400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1986s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1988s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0021788130094549025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2073.52 Core Time (ms) : 2037.42 TIDL Subgraphs Processing Time (ms) : 2034.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 797552005 bytes MEM: Free's : 26 free's of 797552005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1138] | 0 | - | 0.04 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630474c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.371295540090854e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.67 Core Time (ms) : 0.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1399] | 1 | True | 0.12 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363131160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002224413963120852 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.70 Core Time (ms) : 9.41 TIDL Subgraphs Processing Time (ms) : 9.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30190485 bytes MEM: Free's : 26 free's of 30190485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_499] | 1 | True | 0.26 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f467ba50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017035079791019331 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 109.41 Core Time (ms) : 106.23 TIDL Subgraphs Processing Time (ms) : 106.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60572685 bytes MEM: Free's : 26 free's of 60572685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1229] | 1 | True | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363133410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015546699697623108 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 104.04 Core Time (ms) : 103.59 TIDL Subgraphs Processing Time (ms) : 103.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30858637 bytes MEM: Free's : 26 free's of 30858637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1307] | 1 | True | 0.25 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8153630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6017s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00045381928735084966 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 80.92 Core Time (ms) : 75.31 TIDL Subgraphs Processing Time (ms) : 75.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85960693 bytes MEM: Free's : 26 free's of 85960693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_92] | 0 | - | 0.06 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4591d20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 9.75260294984435e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.89 Core Time (ms) : 0.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1141] | 1 | True | 0.65 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614362c04390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10035s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001593796337418106 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 484.41 Core Time (ms) : 479.58 TIDL Subgraphs Processing Time (ms) : 479.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74324573 bytes MEM: Free's : 26 free's of 74324573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_132] | 0 | - | 0.05 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f467f920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.02 Core Time (ms) : 1.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_993] | 1 | True | 0.09 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45e29b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1740s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000139784657987528 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.09 Core Time (ms) : 2.99 TIDL Subgraphs Processing Time (ms) : 2.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14486125 bytes MEM: Free's : 26 free's of 14486125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_831] | 1 | True | 0.11 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8198040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014516064759289375 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.52 Core Time (ms) : 17.34 TIDL Subgraphs Processing Time (ms) : 17.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20554533 bytes MEM: Free's : 26 free's of 20554533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_430] | 1 | True | 0.09 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45983d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004704879012390359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.51 Core Time (ms) : 1.44 TIDL Subgraphs Processing Time (ms) : 1.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14046473 bytes MEM: Free's : 26 free's of 14046473 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_262] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece806dbd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.85 Core Time (ms) : 2.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_737] | 1 | True | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f41a7420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000145176844277999 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 81.00 Core Time (ms) : 80.66 TIDL Subgraphs Processing Time (ms) : 80.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20196699 bytes MEM: Free's : 26 free's of 20196699 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_282] | 0 | - | 0.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8158d50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3392755227254303e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.91 Core Time (ms) : 13.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_953] | 1 | True | 0.12 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8156da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015753250571769187 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.34 Core Time (ms) : 9.99 TIDL Subgraphs Processing Time (ms) : 9.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20806085 bytes MEM: Free's : 26 free's of 20806085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_645] | 1 | True | 0.35 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42cb7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014964075779150542 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 237.16 Core Time (ms) : 235.41 TIDL Subgraphs Processing Time (ms) : 235.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32316365 bytes MEM: Free's : 26 free's of 32316365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1174] | 0 | - | 0.06 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece807b990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.75 Core Time (ms) : 12.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_516] | 1 | True | 0.15 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece815dde0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001525000300271028 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.73 Core Time (ms) : 28.68 TIDL Subgraphs Processing Time (ms) : 28.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38550853 bytes MEM: Free's : 26 free's of 38550853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1107] | 1 | True | 0.15 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630504f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015506846775111227 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.92 Core Time (ms) : 43.52 TIDL Subgraphs Processing Time (ms) : 43.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24530657 bytes MEM: Free's : 26 free's of 24530657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_560] | 1 | True | 0.71 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81653a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016269521814740704 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 511.94 Core Time (ms) : 504.56 TIDL Subgraphs Processing Time (ms) : 504.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157642021 bytes MEM: Free's : 26 free's of 157642021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_622] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e09bc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1278] | 0 | - | 0.04 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e03840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.858585774119384e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_651] | 1 | True | 1.54 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363142cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001590976679618822 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1341.11 Core Time (ms) : 1332.87 TIDL Subgraphs Processing Time (ms) : 1332.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 162302929 bytes MEM: Free's : 26 free's of 162302929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1416] | 0 | - | 0.10 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1ea65880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.67 Core Time (ms) : 11.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1473] | 1 | True | 0.15 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f459fc40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10667s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001486635866486452 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.76 Core Time (ms) : 15.58 TIDL Subgraphs Processing Time (ms) : 15.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17494141 bytes MEM: Free's : 26 free's of 17494141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_608] | 1 | True | 0.21 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e8048d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1555s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015689858027165694 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 111.37 Core Time (ms) : 110.03 TIDL Subgraphs Processing Time (ms) : 109.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34455733 bytes MEM: Free's : 26 free's of 34455733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_747] | 1 | True | 11.90 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f43b4b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016472250973644873 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11545.35 Core Time (ms) : 11528.07 TIDL Subgraphs Processing Time (ms) : 11526.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 426876421 bytes MEM: Free's : 26 free's of 426876421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_984] | 1 | True | 0.37 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a7c2e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6396s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015334036181783586 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 228.45 Core Time (ms) : 224.79 TIDL Subgraphs Processing Time (ms) : 224.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 84776077 bytes MEM: Free's : 26 free's of 84776077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1439] | 1 | True | 0.16 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e71c970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016364767040341963 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.65 Core Time (ms) : 36.18 TIDL Subgraphs Processing Time (ms) : 36.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44328241 bytes MEM: Free's : 26 free's of 44328241 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_256] | 0 | - | 0.03 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e80b7f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1242] | 0 | - | 0.02 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e80c020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_962] | 1 | True | 0.13 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a8aef70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014832340845225963 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.06 Core Time (ms) : 38.07 TIDL Subgraphs Processing Time (ms) : 38.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26819133 bytes MEM: Free's : 26 free's of 26819133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1191] | 1 | True | 0.13 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e71f0d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009610106388899859 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.55 Core Time (ms) : 26.05 TIDL Subgraphs Processing Time (ms) : 26.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20175061 bytes MEM: Free's : 26 free's of 20175061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1224] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece807b150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.546419322226582e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.64 Core Time (ms) : 7.54 TIDL Subgraphs Processing Time (ms) : 7.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14550901 bytes MEM: Free's : 26 free's of 14550901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_164] | 0 | - | 0.05 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e39af80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.0279457129952234e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.75 Core Time (ms) : 2.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_743] | 1 | True | 0.66 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7ca2450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015491813763375044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 550.41 Core Time (ms) : 548.05 TIDL Subgraphs Processing Time (ms) : 547.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60269371 bytes MEM: Free's : 26 free's of 60269371 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1215] | 1 | True | 2.43 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e80a200 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016263963976620002 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2268.08 Core Time (ms) : 2262.12 TIDL Subgraphs Processing Time (ms) : 2262.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 147583761 bytes MEM: Free's : 26 free's of 147583761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1208] | 1 | True | 0.27 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece816d290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001498599398139995 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 168.37 Core Time (ms) : 166.79 TIDL Subgraphs Processing Time (ms) : 166.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38825313 bytes MEM: Free's : 26 free's of 38825313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_20] | 0 | - | 0.04 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1baf80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7455248547494364e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1139] | 1 | True | 0.61 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436313c6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0034961195602624907 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 475.32 Core Time (ms) : 469.05 TIDL Subgraphs Processing Time (ms) : 468.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103761373 bytes MEM: Free's : 26 free's of 103761373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_828] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece807e120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015027044706348496 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.36 Core Time (ms) : 4.18 TIDL Subgraphs Processing Time (ms) : 4.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16849445 bytes MEM: Free's : 26 free's of 16849445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_586] | 0 | - | 0.05 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece816a020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.1770579688237585e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.30 Core Time (ms) : 2.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1420] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece83c9a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_429] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8205460 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1468] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8084500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_47] | 1 | True | 0.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8080630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.052453050143735906 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.03 Core Time (ms) : 0.96 TIDL Subgraphs Processing Time (ms) : 0.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13476245 bytes MEM: Free's : 26 free's of 13476245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1325] | 1 | True | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363183e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006655688198575768 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.18 Core Time (ms) : 17.09 TIDL Subgraphs Processing Time (ms) : 17.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19989873 bytes MEM: Free's : 26 free's of 19989873 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1206] | 0 | - | 0.04 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630582b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.82 Core Time (ms) : 3.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_972] | 1 | True | 0.11 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436305eb00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001654047041920773 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.75 Core Time (ms) : 27.54 TIDL Subgraphs Processing Time (ms) : 27.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39832681 bytes MEM: Free's : 26 free's of 39832681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_323] | 1 | True | 0.08 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e71a910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1214s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014377550052617586 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.97 Core Time (ms) : 1.87 TIDL Subgraphs Processing Time (ms) : 1.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14889609 bytes MEM: Free's : 26 free's of 14889609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_748] | 0 | - | 0.03 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e477210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.61 Core Time (ms) : 0.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1219] | 1 | True | 0.31 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e80f850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5967s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016472955402429648 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 214.38 Core Time (ms) : 213.57 TIDL Subgraphs Processing Time (ms) : 213.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34615157 bytes MEM: Free's : 26 free's of 34615157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_843] | 1 | True | 0.09 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e72c2c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1220s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0036990702817729275 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.21 Core Time (ms) : 7.99 TIDL Subgraphs Processing Time (ms) : 7.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23380581 bytes MEM: Free's : 26 free's of 23380581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_615] | 1 | True | 2.99 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e39c930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001625632349503672 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2571.10 Core Time (ms) : 2547.20 TIDL Subgraphs Processing Time (ms) : 2546.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 453600761 bytes MEM: Free's : 26 free's of 453600761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_104] | 0 | - | 0.05 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e875d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3944232341695281e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_246] | 1 | True | 0.18 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e8a5e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1753s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001683025015824162 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 95.02 Core Time (ms) : 94.43 TIDL Subgraphs Processing Time (ms) : 94.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29328621 bytes MEM: Free's : 26 free's of 29328621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1244] | 1 | True | 0.14 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686ab3a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014300090819738373 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.95 Core Time (ms) : 55.79 TIDL Subgraphs Processing Time (ms) : 55.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18564985 bytes MEM: Free's : 26 free's of 18564985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_535] | 1 | True | 0.17 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b98dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015289959265938174 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 76.92 Core Time (ms) : 75.72 TIDL Subgraphs Processing Time (ms) : 75.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39922939 bytes MEM: Free's : 26 free's of 39922939 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_375] | 1 | True | 0.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164da0590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004273591718915316 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.82 Core Time (ms) : 22.68 TIDL Subgraphs Processing Time (ms) : 22.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20048665 bytes MEM: Free's : 26 free's of 20048665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1340] | 1 | True | 0.13 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164da24c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015775714399918472 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.06 Core Time (ms) : 22.87 TIDL Subgraphs Processing Time (ms) : 22.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21864517 bytes MEM: Free's : 26 free's of 21864517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1027] | 1 | True | 0.18 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164da3cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017750690267753484 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.02 Core Time (ms) : 38.90 TIDL Subgraphs Processing Time (ms) : 38.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73169453 bytes MEM: Free's : 26 free's of 73169453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_343] | 1 | True | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e903f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0010997266342815672 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.57 Core Time (ms) : 89.24 TIDL Subgraphs Processing Time (ms) : 89.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61573397 bytes MEM: Free's : 26 free's of 61573397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_232] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c11d50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_339] | 1 | True | 0.54 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686bedcd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00022121984851274342 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 366.76 Core Time (ms) : 358.11 TIDL Subgraphs Processing Time (ms) : 358.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 162342077 bytes MEM: Free's : 26 free's of 162342077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_250] | 1 | True | 0.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164dac2b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013841090777745642 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.42 Core Time (ms) : 25.28 TIDL Subgraphs Processing Time (ms) : 25.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18038913 bytes MEM: Free's : 26 free's of 18038913 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_614] | 0 | - | 0.05 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e11649639f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.5499287974145152e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.41 Core Time (ms) : 7.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1339] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686afc5d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_861] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686afb7f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1198] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686903f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.881426461971336e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.91 Core Time (ms) : 0.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_368] | 1 | True | 0.17 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686afda60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005432655749553724 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.41 Core Time (ms) : 68.95 TIDL Subgraphs Processing Time (ms) : 68.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41048597 bytes MEM: Free's : 26 free's of 41048597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_619] | 1 | True | 0.68 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f6866b4a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1504s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016179163345259558 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 552.54 Core Time (ms) : 548.40 TIDL Subgraphs Processing Time (ms) : 548.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88953517 bytes MEM: Free's : 26 free's of 88953517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1087] | 1 | True | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e819be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001665631710486968 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 170.87 Core Time (ms) : 168.12 TIDL Subgraphs Processing Time (ms) : 168.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71934944 bytes MEM: Free's : 26 free's of 71934944 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_863] | 0 | - | 0.05 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e817c00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.26 Core Time (ms) : 3.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1050] | 0 | - | 0.02 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e72ec80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 7.539507033981001e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_377] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c379b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1222s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015228612804534685 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.71 Core Time (ms) : 40.60 TIDL Subgraphs Processing Time (ms) : 40.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20008817 bytes MEM: Free's : 26 free's of 20008817 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_65] | 1 | True | 0.10 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b039e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001351853014688825 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.90 Core Time (ms) : 6.55 TIDL Subgraphs Processing Time (ms) : 6.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22858517 bytes MEM: Free's : 26 free's of 22858517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_316] | 1 | True | 0.15 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b06cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011189867111346993 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.34 Core Time (ms) : 37.39 TIDL Subgraphs Processing Time (ms) : 37.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74159433 bytes MEM: Free's : 26 free's of 74159433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_773] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b09980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5917s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013719066119904658 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.28 Core Time (ms) : 2.19 TIDL Subgraphs Processing Time (ms) : 2.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13681261 bytes MEM: Free's : 26 free's of 13681261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_169] | 1 | True | 0.70 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46909c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015927800609574812 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 563.49 Core Time (ms) : 559.74 TIDL Subgraphs Processing Time (ms) : 559.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 95554677 bytes MEM: Free's : 26 free's of 95554677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1398] | 1 | True | 0.15 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f468e9b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001811475657834169 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.52 Core Time (ms) : 20.50 TIDL Subgraphs Processing Time (ms) : 20.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57388053 bytes MEM: Free's : 26 free's of 57388053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1373] | 1 | True | 2.83 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f41acd60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017320670377246784 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2366.54 Core Time (ms) : 2337.86 TIDL Subgraphs Processing Time (ms) : 2336.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 617505333 bytes MEM: Free's : 26 free's of 617505333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1021] | 1 | True | 0.10 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45ac650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.34453835494050095 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.10 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20472185 bytes MEM: Free's : 26 free's of 20472185 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_659] | 1 | True | 0.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45ae740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2139s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012792543321619575 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.24 Core Time (ms) : 2.17 TIDL Subgraphs Processing Time (ms) : 2.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13988373 bytes MEM: Free's : 26 free's of 13988373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_128] | 0 | - | 0.05 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f486d320 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3199400954502915e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1463] | 1 | True | 0.68 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4698340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5888s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003726733204220229 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 465.82 Core Time (ms) : 456.73 TIDL Subgraphs Processing Time (ms) : 456.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 233362189 bytes MEM: Free's : 26 free's of 233362189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_183] | 1 | True | 0.53 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f433aac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.153s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015922079310436724 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 382.54 Core Time (ms) : 378.86 TIDL Subgraphs Processing Time (ms) : 378.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 99079989 bytes MEM: Free's : 26 free's of 99079989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_656] | 1 | True | 0.10 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4719bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013290525476697233 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.29 Core Time (ms) : 3.17 TIDL Subgraphs Processing Time (ms) : 3.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15200397 bytes MEM: Free's : 26 free's of 15200397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1251] | 1 | True | 1.91 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42cb680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016572715178732358 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1781.97 Core Time (ms) : 1778.34 TIDL Subgraphs Processing Time (ms) : 1778.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107833177 bytes MEM: Free's : 26 free's of 107833177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1199] | 1 | True | 0.15 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45bc750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007042644053260215 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.65 Core Time (ms) : 51.73 TIDL Subgraphs Processing Time (ms) : 51.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35018769 bytes MEM: Free's : 26 free's of 35018769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_853] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45bbdc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014655611624388824 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.57 Core Time (ms) : 5.40 TIDL Subgraphs Processing Time (ms) : 5.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17481557 bytes MEM: Free's : 26 free's of 17481557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_299] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45bd2f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.137s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2155s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2156s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016250603086446548 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.06 Core Time (ms) : 2.92 TIDL Subgraphs Processing Time (ms) : 2.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23222405 bytes MEM: Free's : 26 free's of 23222405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_631] | 1 | True | 0.60 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46a9380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001602467827866451 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 454.63 Core Time (ms) : 450.47 TIDL Subgraphs Processing Time (ms) : 450.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107859349 bytes MEM: Free's : 26 free's of 107859349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_18] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46ab360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016141003438246014 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.00 Core Time (ms) : 10.62 TIDL Subgraphs Processing Time (ms) : 10.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31330053 bytes MEM: Free's : 26 free's of 31330053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_425] | 0 | - | 0.05 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46ef220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1267] | 1 | True | 1.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46ad560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00245999443633642 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1053.54 Core Time (ms) : 1050.86 TIDL Subgraphs Processing Time (ms) : 1050.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 78060757 bytes MEM: Free's : 26 free's of 78060757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1258] | 0 | - | 0.04 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f4812ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.169605195796394e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_487] | 1 | True | 0.53 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d387f8dad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0032147951159455846 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 404.16 Core Time (ms) : 400.72 TIDL Subgraphs Processing Time (ms) : 400.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85582273 bytes MEM: Free's : 26 free's of 85582273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1321] | 1 | True | 0.09 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9a74f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.422578159295579e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.85 Core Time (ms) : 2.70 TIDL Subgraphs Processing Time (ms) : 2.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15269541 bytes MEM: Free's : 26 free's of 15269541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_305] | 1 | True | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9a78f50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007412448268132783 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.57 Core Time (ms) : 31.91 TIDL Subgraphs Processing Time (ms) : 31.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81560821 bytes MEM: Free's : 26 free's of 81560821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1427] | 1 | True | 0.12 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b64100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003259745966172647 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.03 Core Time (ms) : 16.30 TIDL Subgraphs Processing Time (ms) : 16.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38851517 bytes MEM: Free's : 26 free's of 38851517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_497] | 1 | True | 0.15 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b69090 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017750207380280914 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.10 Core Time (ms) : 35.11 TIDL Subgraphs Processing Time (ms) : 35.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75300101 bytes MEM: Free's : 26 free's of 75300101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_257] | 1 | True | 2.49 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3880fcb90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.143s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0037729786991383893 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2320.24 Core Time (ms) : 2314.88 TIDL Subgraphs Processing Time (ms) : 2314.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 122433585 bytes MEM: Free's : 26 free's of 122433585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_5] | 1 | True | 0.22 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9a7fc10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1223s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1225s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011517822464478358 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.70 Core Time (ms) : 48.78 TIDL Subgraphs Processing Time (ms) : 48.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 114304109 bytes MEM: Free's : 26 free's of 114304109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_683] | 1 | True | 5.12 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b987fe70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016685580134431029 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4787.07 Core Time (ms) : 4772.56 TIDL Subgraphs Processing Time (ms) : 4772.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 292736061 bytes MEM: Free's : 26 free's of 292736061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1379] | 0 | - | 0.02 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8007e58c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 7.902119030719974e-16 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_955] | 1 | True | 0.18 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8007dfc70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016766447607871374 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.38 Core Time (ms) : 43.36 TIDL Subgraphs Processing Time (ms) : 43.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 94907997 bytes MEM: Free's : 26 free's of 94907997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1367] | 1 | True | 0.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8007e4b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1228s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015270322389057488 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.38 Core Time (ms) : 19.20 TIDL Subgraphs Processing Time (ms) : 19.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17659765 bytes MEM: Free's : 26 free's of 17659765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1299] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e76dcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015875629115647197 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.73 Core Time (ms) : 15.15 TIDL Subgraphs Processing Time (ms) : 15.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27496677 bytes MEM: Free's : 26 free's of 27496677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_727] | 1 | True | 0.38 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae800ba7b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015334035451561838 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 274.73 Core Time (ms) : 273.81 TIDL Subgraphs Processing Time (ms) : 273.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35786341 bytes MEM: Free's : 26 free's of 35786341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1063] | 1 | True | 0.25 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e771670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0010885484056945588 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 131.38 Core Time (ms) : 128.38 TIDL Subgraphs Processing Time (ms) : 128.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72046261 bytes MEM: Free's : 26 free's of 72046261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1403] | 1 | True | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77725710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001839442758487889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 143.14 Core Time (ms) : 135.19 TIDL Subgraphs Processing Time (ms) : 135.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 167767301 bytes MEM: Free's : 26 free's of 167767301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_507] | 1 | True | 0.12 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008ce100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015951121532569132 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.84 Core Time (ms) : 22.74 TIDL Subgraphs Processing Time (ms) : 22.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42459189 bytes MEM: Free's : 26 free's of 42459189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_12] | 0 | - | 0.05 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77725c80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.6229374750417455e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.34 Core Time (ms) : 2.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1255] | 1 | True | 1.30 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77724f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002907209260054518 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1173.08 Core Time (ms) : 1170.05 TIDL Subgraphs Processing Time (ms) : 1169.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76528741 bytes MEM: Free's : 26 free's of 76528741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_939] | 1 | True | 0.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c41a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1870s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018424641844463427 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.36 Core Time (ms) : 1.28 TIDL Subgraphs Processing Time (ms) : 1.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14248461 bytes MEM: Free's : 26 free's of 14248461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_82] | 1 | True | 0.12 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d2fa90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014794850169217298 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.67 Core Time (ms) : 34.78 TIDL Subgraphs Processing Time (ms) : 34.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34602693 bytes MEM: Free's : 26 free's of 34602693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1446] | 1 | True | 0.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d2f440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1489s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002020080584380924 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.10 Core Time (ms) : 20.67 TIDL Subgraphs Processing Time (ms) : 20.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24292113 bytes MEM: Free's : 26 free's of 24292113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_137] | 1 | True | 4.56 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f50909cebe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0009291081227018504 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3991.19 Core Time (ms) : 3961.91 TIDL Subgraphs Processing Time (ms) : 3960.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 661915589 bytes MEM: Free's : 26 free's of 661915589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_874] | 1 | True | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb0efa70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6035s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015720736810342377 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 72.90 Core Time (ms) : 71.24 TIDL Subgraphs Processing Time (ms) : 71.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39563681 bytes MEM: Free's : 26 free's of 39563681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_977] | 0 | - | 0.04 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4132e10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.76 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_817] | 1 | True | 0.16 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb0f25a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6001s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00010205826047365651 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.56 Core Time (ms) : 22.60 TIDL Subgraphs Processing Time (ms) : 22.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65065061 bytes MEM: Free's : 26 free's of 65065061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_949] | 1 | True | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4138be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001789008671686429 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.42 Core Time (ms) : 50.83 TIDL Subgraphs Processing Time (ms) : 50.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65230173 bytes MEM: Free's : 26 free's of 65230173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_213] | 1 | True | 0.07 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1e2150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009140226950824245 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.39 Core Time (ms) : 5.26 TIDL Subgraphs Processing Time (ms) : 5.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15546187 bytes MEM: Free's : 26 free's of 15546187 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_981] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb404e3c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_472] | 1 | True | 0.09 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb404e270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1471s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015973214694736416 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.50 Core Time (ms) : 15.17 TIDL Subgraphs Processing Time (ms) : 15.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19348373 bytes MEM: Free's : 26 free's of 19348373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1247] | 1 | True | 1.13 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1e0930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015690060032649258 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1002.57 Core Time (ms) : 998.95 TIDL Subgraphs Processing Time (ms) : 998.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89068635 bytes MEM: Free's : 26 free's of 89068635 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_515] | 1 | True | 0.11 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb404f3d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1795s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014028687181621643 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.64 Core Time (ms) : 11.12 TIDL Subgraphs Processing Time (ms) : 11.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26627629 bytes MEM: Free's : 26 free's of 26627629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_556] | 1 | True | 0.09 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da615c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012985002799917545 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.66 Core Time (ms) : 2.51 TIDL Subgraphs Processing Time (ms) : 2.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14831997 bytes MEM: Free's : 26 free's of 14831997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1276] | 0 | - | 0.03 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40a0920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_410] | 1 | True | 0.09 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4054570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014763677288572336 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.80 Core Time (ms) : 5.69 TIDL Subgraphs Processing Time (ms) : 5.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18278201 bytes MEM: Free's : 26 free's of 18278201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_3] | 1 | True | 0.13 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884b8540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1203s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1205s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017823736881839925 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.15 Core Time (ms) : 26.39 TIDL Subgraphs Processing Time (ms) : 26.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59955998 bytes MEM: Free's : 26 free's of 59955998 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1172] | 1 | True | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3bb1370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015161218300672644 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 89.39 Core Time (ms) : 88.22 TIDL Subgraphs Processing Time (ms) : 88.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34888625 bytes MEM: Free's : 26 free's of 34888625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1366] | 1 | True | 0.71 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d387f8dbd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.132s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6039s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015841027620660094 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 536.11 Core Time (ms) : 528.10 TIDL Subgraphs Processing Time (ms) : 527.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 120210789 bytes MEM: Free's : 26 free's of 120210789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_144] | 0 | - | 0.03 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77640450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3576348996704672e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_718] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4059640 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.897740282512611e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_899] | 1 | True | 0.09 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc39cb80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1594s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014373590070338048 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.51 Core Time (ms) : 9.42 TIDL Subgraphs Processing Time (ms) : 9.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14342509 bytes MEM: Free's : 26 free's of 14342509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_784] | 0 | - | 0.04 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7776b660 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1120] | 1 | True | 0.08 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb414d7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03204404825516676 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.05 Core Time (ms) : 4.02 TIDL Subgraphs Processing Time (ms) : 4.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12595509 bytes MEM: Free's : 26 free's of 12595509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1008] | 1 | True | 0.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7776c3f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1291s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016367539608995503 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.89 Core Time (ms) : 7.78 TIDL Subgraphs Processing Time (ms) : 7.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20965984 bytes MEM: Free's : 26 free's of 20965984 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_822] | 1 | True | 0.09 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4045190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.519902082109792e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.15 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 1.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13708181 bytes MEM: Free's : 26 free's of 13708181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_22] | 1 | True | 0.84 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc32bbb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5159s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018152096397154702 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 516.72 Core Time (ms) : 503.56 TIDL Subgraphs Processing Time (ms) : 503.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 255832019 bytes MEM: Free's : 26 free's of 255832019 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_896] | 1 | True | 0.15 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77645070 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015816095115472406 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.49 Core Time (ms) : 52.35 TIDL Subgraphs Processing Time (ms) : 52.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21659477 bytes MEM: Free's : 26 free's of 21659477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_254] | 0 | - | 0.05 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb414a840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.323556458954191e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.17 Core Time (ms) : 6.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_640] | 1 | True | 0.13 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4060670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015459423284154656 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.43 Core Time (ms) : 46.25 TIDL Subgraphs Processing Time (ms) : 46.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20227451 bytes MEM: Free's : 26 free's of 20227451 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_636] | 1 | True | 0.07 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77644b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1584s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1586s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.000274486883721e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.90 Core Time (ms) : 2.82 TIDL Subgraphs Processing Time (ms) : 2.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14192533 bytes MEM: Free's : 26 free's of 14192533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1360] | 0 | - | 0.02 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77648c10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_911] | 1 | True | 1.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4149220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002452922861028459 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 474.08 Core Time (ms) : 439.49 TIDL Subgraphs Processing Time (ms) : 438.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 588257473 bytes MEM: Free's : 26 free's of 588257473 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_495] | 1 | True | 0.45 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda777325a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001895815332253496 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 143.11 Core Time (ms) : 128.04 TIDL Subgraphs Processing Time (ms) : 127.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 302271821 bytes MEM: Free's : 26 free's of 302271821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1363] | 1 | True | 1.55 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884bb5d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0031691003168664417 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1222.87 Core Time (ms) : 1207.77 TIDL Subgraphs Processing Time (ms) : 1207.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 338960421 bytes MEM: Free's : 26 free's of 338960421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_86] | 1 | True | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1e5050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5978s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5981s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001507282612090947 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 63.05 Core Time (ms) : 61.02 TIDL Subgraphs Processing Time (ms) : 60.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37872453 bytes MEM: Free's : 26 free's of 37872453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_357] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb0fbc60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_476] | 1 | True | 0.40 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1050e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015865481434946087 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 237.32 Core Time (ms) : 233.30 TIDL Subgraphs Processing Time (ms) : 233.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88881421 bytes MEM: Free's : 26 free's of 88881421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1036] | 1 | True | 0.33 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008d8f60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4770s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4772s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015840539653492816 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 186.68 Core Time (ms) : 183.71 TIDL Subgraphs Processing Time (ms) : 183.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63081781 bytes MEM: Free's : 26 free's of 63081781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_632] | 1 | True | 0.14 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7764d210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.565202113555435e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.14 Core Time (ms) : 45.81 TIDL Subgraphs Processing Time (ms) : 45.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24471509 bytes MEM: Free's : 26 free's of 24471509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_596] | 1 | True | 0.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae967f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013070322094507173 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.47 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12746997 bytes MEM: Free's : 26 free's of 12746997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_574] | 0 | - | 0.11 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77734f10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4112850960525063e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.98 Core Time (ms) : 3.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_508] | 1 | True | 0.14 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ae97570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001585992813290367 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.81 Core Time (ms) : 26.97 TIDL Subgraphs Processing Time (ms) : 26.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32725721 bytes MEM: Free's : 26 free's of 32725721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_512] | 1 | True | 0.15 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af83490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.170s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016122996991687927 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.34 Core Time (ms) : 25.46 TIDL Subgraphs Processing Time (ms) : 25.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37455497 bytes MEM: Free's : 26 free's of 37455497 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_467] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009503c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2004s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005730957078828954 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.00 Core Time (ms) : 2.90 TIDL Subgraphs Processing Time (ms) : 2.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14417869 bytes MEM: Free's : 26 free's of 14417869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_699] | 1 | True | 1.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1e74d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1572s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015445962897323625 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1034.29 Core Time (ms) : 1031.17 TIDL Subgraphs Processing Time (ms) : 1031.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71977568 bytes MEM: Free's : 26 free's of 71977568 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1046] | 0 | - | 0.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc007f3350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1051] | 1 | True | 0.28 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af862e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00035325804963629113 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 141.07 Core Time (ms) : 137.80 TIDL Subgraphs Processing Time (ms) : 137.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 84420277 bytes MEM: Free's : 26 free's of 84420277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_387] | 0 | - | 0.05 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc003463c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.16 Core Time (ms) : 5.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_247] | 1 | True | 0.60 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c323779da20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0015270255011035486 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 430.27 Core Time (ms) : 427.66 TIDL Subgraphs Processing Time (ms) : 427.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62448593 bytes MEM: Free's : 26 free's of 62448593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1384] | 1 | True | 0.29 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008ded60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0039863837598639665 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 185.46 Core Time (ms) : 184.72 TIDL Subgraphs Processing Time (ms) : 184.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30852673 bytes MEM: Free's : 26 free's of 30852673 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_783] | 1 | True | 0.08 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40612c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017437739416099356 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.41 Core Time (ms) : 3.08 TIDL Subgraphs Processing Time (ms) : 3.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19487881 bytes MEM: Free's : 26 free's of 19487881 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_106] | 1 | True | 0.21 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af90d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015288969399814123 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 116.10 Core Time (ms) : 114.53 TIDL Subgraphs Processing Time (ms) : 114.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 45418200 bytes MEM: Free's : 26 free's of 45418200 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1407] | 1 | True | 0.13 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb414d460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1996s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1998s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015169743291234444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.91 Core Time (ms) : 22.01 TIDL Subgraphs Processing Time (ms) : 21.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33781417 bytes MEM: Free's : 26 free's of 33781417 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_242] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0089ced0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013406915174050965 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.13 Core Time (ms) : 14.96 TIDL Subgraphs Processing Time (ms) : 14.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15018473 bytes MEM: Free's : 26 free's of 15018473 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_639] | 1 | True | 6.20 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00601880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016388526527299544 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5763.36 Core Time (ms) : 5744.22 TIDL Subgraphs Processing Time (ms) : 5742.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 438566093 bytes MEM: Free's : 26 free's of 438566093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1409] | 1 | True | 0.65 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af8b470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001662267380805361 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 402.33 Core Time (ms) : 394.14 TIDL Subgraphs Processing Time (ms) : 394.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 190294213 bytes MEM: Free's : 26 free's of 190294213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_449] | 1 | True | 0.19 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4153e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0014289049806389634 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.14 Core Time (ms) : 53.24 TIDL Subgraphs Processing Time (ms) : 53.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38853821 bytes MEM: Free's : 26 free's of 38853821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_670] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e51e10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.4099412140703905e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_373] | 1 | True | 0.50 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c21fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00424251147374247 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 310.25 Core Time (ms) : 304.13 TIDL Subgraphs Processing Time (ms) : 304.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 115519729 bytes MEM: Free's : 26 free's of 115519729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1007] | 1 | True | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f36350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001593404010200389 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 124.39 Core Time (ms) : 119.86 TIDL Subgraphs Processing Time (ms) : 119.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 104858316 bytes MEM: Free's : 26 free's of 104858316 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1180] | 1 | True | 0.15 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb406b840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02479758959554633 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.48 Core Time (ms) : 40.74 TIDL Subgraphs Processing Time (ms) : 40.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29196277 bytes MEM: Free's : 26 free's of 29196277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1077] | 1 | True | 0.09 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883d7dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.815890812072603e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.49 Core Time (ms) : 7.36 TIDL Subgraphs Processing Time (ms) : 7.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21319413 bytes MEM: Free's : 26 free's of 21319413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_312] | 0 | - | 0.05 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4157950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_261] | 1 | True | 0.18 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883db9a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007637020816078256 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.61 Core Time (ms) : 55.29 TIDL Subgraphs Processing Time (ms) : 55.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23794805 bytes MEM: Free's : 26 free's of 23794805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1246] | 0 | - | 0.03 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb415ddf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_675] | 1 | True | 2.16 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb41587b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000157639240231622 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1984.19 Core Time (ms) : 1977.16 TIDL Subgraphs Processing Time (ms) : 1977.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 143852533 bytes MEM: Free's : 26 free's of 143852533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_786] | 1 | True | 0.15 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e4f7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00020730502694704266 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.67 Core Time (ms) : 20.64 TIDL Subgraphs Processing Time (ms) : 20.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36860537 bytes MEM: Free's : 26 free's of 36860537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_384] | 1 | True | 0.12 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884c4e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000141107892513922 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.55 Core Time (ms) : 31.39 TIDL Subgraphs Processing Time (ms) : 31.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18548813 bytes MEM: Free's : 26 free's of 18548813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_723] | 1 | True | 0.12 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1f1750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001464277337810943 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.55 Core Time (ms) : 11.27 TIDL Subgraphs Processing Time (ms) : 11.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17189973 bytes MEM: Free's : 26 free's of 17189973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_231] | 1 | True | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f468e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013339242574129744 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.87 Core Time (ms) : 1.85 TIDL Subgraphs Processing Time (ms) : 1.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12548059 bytes MEM: Free's : 26 free's of 12548059 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1262] | 0 | - | 0.05 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d0d860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3632968565563189e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.09 Core Time (ms) : 1.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1389] | 1 | True | 0.31 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d387f8f6c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016982000593875927 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 206.32 Core Time (ms) : 204.22 TIDL Subgraphs Processing Time (ms) : 204.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50507077 bytes MEM: Free's : 26 free's of 50507077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_157] | 1 | True | 1.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d16500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016016376479153759 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1056.21 Core Time (ms) : 1047.33 TIDL Subgraphs Processing Time (ms) : 1047.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 109330089 bytes MEM: Free's : 26 free's of 109330089 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_540] | 1 | True | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1ecee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001551724994096807 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.36 Core Time (ms) : 65.39 TIDL Subgraphs Processing Time (ms) : 65.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36494288 bytes MEM: Free's : 26 free's of 36494288 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1108] | 1 | True | 0.13 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e56dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02263669913391164 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.92 Core Time (ms) : 25.47 TIDL Subgraphs Processing Time (ms) : 25.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21723365 bytes MEM: Free's : 26 free's of 21723365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_970] | 1 | True | 0.14 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9a83210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015928529223043677 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.92 Core Time (ms) : 39.48 TIDL Subgraphs Processing Time (ms) : 39.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24967333 bytes MEM: Free's : 26 free's of 24967333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1226] | 0 | - | 0.02 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a911aa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 3.955575117668891e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.60 Core Time (ms) : 0.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1428] | 1 | True | 0.11 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f3be80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011345905408399841 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.61 Core Time (ms) : 7.20 TIDL Subgraphs Processing Time (ms) : 7.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21004829 bytes MEM: Free's : 26 free's of 21004829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1290] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a805ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017331215757136753 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.94 Core Time (ms) : 3.80 TIDL Subgraphs Processing Time (ms) : 3.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19176861 bytes MEM: Free's : 26 free's of 19176861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1016] | 1 | True | 0.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b6dfd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016201625277549353 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.41 Core Time (ms) : 14.85 TIDL Subgraphs Processing Time (ms) : 14.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31634453 bytes MEM: Free's : 26 free's of 31634453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_584] | 1 | True | 0.09 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1055a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014587402779583583 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.54 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12706821 bytes MEM: Free's : 26 free's of 12706821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_990] | 1 | True | 0.17 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a935550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001464163789992704 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.19 Core Time (ms) : 50.94 TIDL Subgraphs Processing Time (ms) : 50.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20125621 bytes MEM: Free's : 26 free's of 20125621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_197] | 1 | True | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e5a320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029578994136357085 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.30 Core Time (ms) : 67.98 TIDL Subgraphs Processing Time (ms) : 67.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24076001 bytes MEM: Free's : 26 free's of 24076001 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1256] | 0 | - | 0.09 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884cc000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 29.78 Core Time (ms) : 29.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_253] | 1 | True | 0.44 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b70100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015630608049165687 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 309.73 Core Time (ms) : 308.76 TIDL Subgraphs Processing Time (ms) : 308.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30617661 bytes MEM: Free's : 26 free's of 30617661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1449] | 1 | True | 0.32 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f4c4b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001626835897545539 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 184.81 Core Time (ms) : 180.61 TIDL Subgraphs Processing Time (ms) : 180.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 82956829 bytes MEM: Free's : 26 free's of 82956829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_710] | 0 | - | 0.04 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a8f8a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.653780008745444e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.07 Core Time (ms) : 1.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_460] | 1 | True | 0.29 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a816400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015479399126129635 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 118.96 Core Time (ms) : 112.68 TIDL Subgraphs Processing Time (ms) : 112.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 117994445 bytes MEM: Free's : 26 free's of 117994445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_887] | 0 | - | 0.06 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97cfe40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.66 Core Time (ms) : 2.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_840] | 1 | True | 0.16 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f46e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015963305655634593 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.36 Core Time (ms) : 52.81 TIDL Subgraphs Processing Time (ms) : 52.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39001125 bytes MEM: Free's : 26 free's of 39001125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_37] | 1 | True | 3.42 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b81300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1949s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0030836891046771343 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2770.87 Core Time (ms) : 2733.05 TIDL Subgraphs Processing Time (ms) : 2730.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 828357305 bytes MEM: Free's : 26 free's of 828357305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1257] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a934610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.745332637183146e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.75 Core Time (ms) : 3.70 TIDL Subgraphs Processing Time (ms) : 3.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13343173 bytes MEM: Free's : 26 free's of 13343173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1212] | 1 | True | 0.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689ebac60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.013548673952312225 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 176.80 Core Time (ms) : 175.45 TIDL Subgraphs Processing Time (ms) : 175.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38065889 bytes MEM: Free's : 26 free's of 38065889 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1413] | 1 | True | 0.19 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f50909cf060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001512982125534239 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 97.48 Core Time (ms) : 96.41 TIDL Subgraphs Processing Time (ms) : 96.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32921969 bytes MEM: Free's : 26 free's of 32921969 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1052] | 1 | True | 0.18 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a818af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011889335893404446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.36 Core Time (ms) : 46.49 TIDL Subgraphs Processing Time (ms) : 46.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48274649 bytes MEM: Free's : 26 free's of 48274649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_185] | 1 | True | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e66f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008560540472927411 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 110.96 Core Time (ms) : 109.49 TIDL Subgraphs Processing Time (ms) : 109.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35845905 bytes MEM: Free's : 26 free's of 35845905 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_263] | 1 | True | 0.93 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a54a1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016115323507830714 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 741.74 Core Time (ms) : 738.09 TIDL Subgraphs Processing Time (ms) : 738.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 84650981 bytes MEM: Free's : 26 free's of 84650981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1272] | 0 | - | 0.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a20c750 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.89 Core Time (ms) : 11.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_493] | 0 | - | 0.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f509098f6d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.30 Core Time (ms) : 18.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_413] | 1 | True | 0.38 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d12e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015708482248487176 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 231.88 Core Time (ms) : 229.47 TIDL Subgraphs Processing Time (ms) : 229.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54497069 bytes MEM: Free's : 26 free's of 54497069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1469] | 1 | True | 0.11 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a11d3b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015104796030703584 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.64 Core Time (ms) : 22.07 TIDL Subgraphs Processing Time (ms) : 22.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24313453 bytes MEM: Free's : 26 free's of 24313453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_618] | 0 | - | 0.05 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c4e4e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.03 Core Time (ms) : 19.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_116] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7da0c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4337075316320833e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.97 Core Time (ms) : 3.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_609] | 1 | True | 0.98 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7da13a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015989292408643383 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 789.39 Core Time (ms) : 782.96 TIDL Subgraphs Processing Time (ms) : 782.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 127766277 bytes MEM: Free's : 26 free's of 127766277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1266] | 0 | - | 0.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f50909810b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.19 Core Time (ms) : 3.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_963] | 1 | True | 0.19 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f4eb50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001509944503705982 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.74 Core Time (ms) : 69.72 TIDL Subgraphs Processing Time (ms) : 69.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33417421 bytes MEM: Free's : 26 free's of 33417421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_45] | 1 | True | 0.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d3bf10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004686980213586587 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.40 Core Time (ms) : 40.60 TIDL Subgraphs Processing Time (ms) : 40.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25411061 bytes MEM: Free's : 26 free's of 25411061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_641] | 1 | True | 0.16 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e131b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015150278647216398 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 74.91 Core Time (ms) : 74.61 TIDL Subgraphs Processing Time (ms) : 74.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23829045 bytes MEM: Free's : 26 free's of 23829045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_371] | 1 | True | 0.35 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d3d7b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0007855420652534753 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 230.79 Core Time (ms) : 227.67 TIDL Subgraphs Processing Time (ms) : 227.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62603413 bytes MEM: Free's : 26 free's of 62603413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_367] | 0 | - | 0.07 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a125ca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1216] | 1 | True | 0.76 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c32379a94d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015268010327176967 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 648.12 Core Time (ms) : 646.57 TIDL Subgraphs Processing Time (ms) : 646.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41788144 bytes MEM: Free's : 26 free's of 41788144 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_598] | 0 | - | 0.06 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f570e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1084] | 1 | True | 0.58 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f51570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1577s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000157947254715241 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 306.67 Core Time (ms) : 298.01 TIDL Subgraphs Processing Time (ms) : 297.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 172764485 bytes MEM: Free's : 26 free's of 172764485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_830] | 1 | True | 0.26 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a122850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 9.57052307013436e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.18 Core Time (ms) : 53.24 TIDL Subgraphs Processing Time (ms) : 53.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 92349349 bytes MEM: Free's : 26 free's of 92349349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_657] | 1 | True | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630ed920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1719s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001340644963232745 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.00 Core Time (ms) : 9.88 TIDL Subgraphs Processing Time (ms) : 9.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14703241 bytes MEM: Free's : 26 free's of 14703241 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1260] | 0 | - | 0.06 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3db1d80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.85 Core Time (ms) : 1.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_486] | 0 | - | 0.06 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630a2a50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_426] | 1 | True | 0.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a466590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018799669496758064 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.14 Core Time (ms) : 28.72 TIDL Subgraphs Processing Time (ms) : 28.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24978573 bytes MEM: Free's : 26 free's of 24978573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_105] | 1 | True | 0.19 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d3ddc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001598534121782815 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 64.27 Core Time (ms) : 62.78 TIDL Subgraphs Processing Time (ms) : 62.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38037565 bytes MEM: Free's : 26 free's of 38037565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1277] | 1 | True | 1.06 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3d79820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015271302885246928 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 897.74 Core Time (ms) : 893.63 TIDL Subgraphs Processing Time (ms) : 893.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71008125 bytes MEM: Free's : 26 free's of 71008125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_109] | 1 | True | 0.46 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630abdf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6017s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.945012686511217e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 243.80 Core Time (ms) : 235.86 TIDL Subgraphs Processing Time (ms) : 235.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 109329205 bytes MEM: Free's : 26 free's of 109329205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_678] | 0 | - | 0.06 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e7b1b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7133146914793714e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.79 Core Time (ms) : 11.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1423] | 1 | True | 0.15 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a903f50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017765156583279522 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.92 Core Time (ms) : 20.00 TIDL Subgraphs Processing Time (ms) : 19.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59064685 bytes MEM: Free's : 26 free's of 59064685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1252] | 0 | - | 0.05 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d46b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.41 Core Time (ms) : 6.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_366] | 0 | - | 0.05 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a127a80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_101] | 1 | True | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d44d20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015186380479633514 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 97.76 Core Time (ms) : 96.16 TIDL Subgraphs Processing Time (ms) : 96.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33880429 bytes MEM: Free's : 26 free's of 33880429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1470] | 1 | True | 0.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a127010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015822806348049043 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.82 Core Time (ms) : 35.65 TIDL Subgraphs Processing Time (ms) : 35.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30774921 bytes MEM: Free's : 26 free's of 30774921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1097] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e6a7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.020185939006138322 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.87 Core Time (ms) : 2.69 TIDL Subgraphs Processing Time (ms) : 2.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14599249 bytes MEM: Free's : 26 free's of 14599249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1349] | 1 | True | 0.08 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a81bdf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.981835067111048e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.68 Core Time (ms) : 3.52 TIDL Subgraphs Processing Time (ms) : 3.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15248933 bytes MEM: Free's : 26 free's of 15248933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_794] | 1 | True | 0.43 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f55e10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018374085184912192 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 202.47 Core Time (ms) : 191.94 TIDL Subgraphs Processing Time (ms) : 191.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 153593573 bytes MEM: Free's : 26 free's of 153593573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_600] | 1 | True | 0.15 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d16860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001585919114658535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.99 Core Time (ms) : 18.53 TIDL Subgraphs Processing Time (ms) : 18.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21103483 bytes MEM: Free's : 26 free's of 21103483 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1076] | 1 | True | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8179fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015315689703689363 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 75.83 Core Time (ms) : 74.91 TIDL Subgraphs Processing Time (ms) : 74.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25958523 bytes MEM: Free's : 26 free's of 25958523 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_168] | 0 | - | 0.08 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a90bca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.12 Core Time (ms) : 9.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_744] | 1 | True | 2.29 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f509096f730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016021689990768442 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2107.47 Core Time (ms) : 2103.56 TIDL Subgraphs Processing Time (ms) : 2103.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 108737921 bytes MEM: Free's : 26 free's of 108737921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_554] | 0 | - | 0.08 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363191c70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.74 Core Time (ms) : 23.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1343] | 1 | True | 0.42 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a81f210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4970s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017451280394939025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 227.02 Core Time (ms) : 223.05 TIDL Subgraphs Processing Time (ms) : 222.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 104876949 bytes MEM: Free's : 26 free's of 104876949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_754] | 0 | - | 0.05 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237948ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.014725719624596e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.83 Core Time (ms) : 4.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_852] | 1 | True | 0.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630f2a70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014561911662245073 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.55 Core Time (ms) : 3.45 TIDL Subgraphs Processing Time (ms) : 3.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14588265 bytes MEM: Free's : 26 free's of 14588265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_569] | 1 | True | 0.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237edd770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001570429536399861 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.63 Core Time (ms) : 30.65 TIDL Subgraphs Processing Time (ms) : 30.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30387393 bytes MEM: Free's : 26 free's of 30387393 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_455] | 1 | True | 0.26 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630ad8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016233223087029625 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 114.87 Core Time (ms) : 109.36 TIDL Subgraphs Processing Time (ms) : 109.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 113278157 bytes MEM: Free's : 26 free's of 113278157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_88] | 0 | - | 0.04 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237fca080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_285] | 1 | True | 0.13 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48a6fd30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.013256592934201042 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.96 Core Time (ms) : 35.35 TIDL Subgraphs Processing Time (ms) : 35.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24987741 bytes MEM: Free's : 26 free's of 24987741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1418] | 0 | - | 0.06 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a5aada0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.27 Core Time (ms) : 3.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1118] | 0 | - | 0.04 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630ab890 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4948811173216205e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_658] | 0 | - | 0.04 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e71400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.427006380808837e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_324] | 1 | True | 0.16 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631950e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001639387938093386 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 64.36 Core Time (ms) : 63.03 TIDL Subgraphs Processing Time (ms) : 62.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39223925 bytes MEM: Free's : 26 free's of 39223925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_900] | 1 | True | 1.98 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a62a150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015752721104589652 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1802.17 Core Time (ms) : 1795.26 TIDL Subgraphs Processing Time (ms) : 1795.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 181096781 bytes MEM: Free's : 26 free's of 181096781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1] | 1 | True | 0.51 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb415ef60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00019026476137955027 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 173.74 Core Time (ms) : 157.92 TIDL Subgraphs Processing Time (ms) : 157.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 348336869 bytes MEM: Free's : 26 free's of 348336869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_152] | 0 | - | 0.05 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e7bca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_451] | 1 | True | 0.47 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436319e1e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00032540831902165475 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 267.13 Core Time (ms) : 257.72 TIDL Subgraphs Processing Time (ms) : 257.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 207007989 bytes MEM: Free's : 26 free's of 207007989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1031] | 1 | True | 0.12 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4161050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1243s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017135084345535836 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.80 Core Time (ms) : 28.02 TIDL Subgraphs Processing Time (ms) : 27.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37262661 bytes MEM: Free's : 26 free's of 37262661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_44] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363199a50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 7.545171995777153e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_878] | 0 | - | 0.02 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630b5070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_190] | 1 | True | 0.33 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4168800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001521151435846032 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 229.77 Core Time (ms) : 228.16 TIDL Subgraphs Processing Time (ms) : 228.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53766629 bytes MEM: Free's : 26 free's of 53766629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_612] | 1 | True | 0.17 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630b0da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015228527110313866 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 80.25 Core Time (ms) : 79.05 TIDL Subgraphs Processing Time (ms) : 78.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37142029 bytes MEM: Free's : 26 free's of 37142029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_52] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631a0ac0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_308] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630b42f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_902] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631d51b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1233] | 1 | True | 0.17 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61436319f210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014761933844397677 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 88.92 Core Time (ms) : 88.52 TIDL Subgraphs Processing Time (ms) : 88.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30980069 bytes MEM: Free's : 26 free's of 30980069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1460] | 0 | - | 0.04 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb407c480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_4] | 0 | - | 0.03 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb407c630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_273] | 1 | True | 0.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4170c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006681819977635711 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.31 Core Time (ms) : 15.06 TIDL Subgraphs Processing Time (ms) : 15.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19448829 bytes MEM: Free's : 26 free's of 19448829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_689] | 1 | True | 0.16 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363218270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015050385522405636 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.39 Core Time (ms) : 54.79 TIDL Subgraphs Processing Time (ms) : 54.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29890365 bytes MEM: Free's : 26 free's of 29890365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1294] | 1 | True | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4169110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00022745113911429703 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 79.81 Core Time (ms) : 72.98 TIDL Subgraphs Processing Time (ms) : 72.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 105805965 bytes MEM: Free's : 26 free's of 105805965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_604] | 1 | True | 0.89 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b979fee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017041667755707577 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 725.95 Core Time (ms) : 719.98 TIDL Subgraphs Processing Time (ms) : 719.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 138706373 bytes MEM: Free's : 26 free's of 138706373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_29] | 1 | True | 0.11 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630b9f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011112965074121342 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.36 Core Time (ms) : 9.39 TIDL Subgraphs Processing Time (ms) : 9.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31975632 bytes MEM: Free's : 26 free's of 31975632 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_627] | 1 | True | 0.11 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630bc8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1574s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001448437604621863 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.53 Core Time (ms) : 24.35 TIDL Subgraphs Processing Time (ms) : 24.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20960685 bytes MEM: Free's : 26 free's of 20960685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1259] | 1 | True | 0.80 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3d81a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4077s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00402679181205763 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 686.65 Core Time (ms) : 684.96 TIDL Subgraphs Processing Time (ms) : 684.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48378376 bytes MEM: Free's : 26 free's of 48378376 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_464] | 1 | True | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143632248f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009056964707957324 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.40 Core Time (ms) : 10.28 TIDL Subgraphs Processing Time (ms) : 10.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18548445 bytes MEM: Free's : 26 free's of 18548445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1239] | 1 | True | 0.67 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631adfd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016565956850705629 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 547.17 Core Time (ms) : 545.10 TIDL Subgraphs Processing Time (ms) : 545.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60955705 bytes MEM: Free's : 26 free's of 60955705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1066] | 0 | - | 0.04 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c5d200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.74 Core Time (ms) : 4.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1306] | 1 | True | 0.07 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c5d9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1380s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04659569426057376 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.29 Core Time (ms) : 1.23 TIDL Subgraphs Processing Time (ms) : 1.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13999193 bytes MEM: Free's : 26 free's of 13999193 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1117] | 1 | True | 0.11 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c5fce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1391s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016029491873545878 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.07 Core Time (ms) : 31.37 TIDL Subgraphs Processing Time (ms) : 31.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25398825 bytes MEM: Free's : 26 free's of 25398825 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1157] | 1 | True | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d56560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000155706347976781 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 122.26 Core Time (ms) : 120.93 TIDL Subgraphs Processing Time (ms) : 120.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51970750 bytes MEM: Free's : 26 free's of 51970750 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1222] | 0 | - | 0.02 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a823f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.067000866880897e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_266] | 0 | - | 0.05 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a426a50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.906410965778043e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.46 Core Time (ms) : 1.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_916] | 1 | True | 1.91 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a90fec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001681298737073234 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1351.55 Core Time (ms) : 1308.56 TIDL Subgraphs Processing Time (ms) : 1307.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 657141197 bytes MEM: Free's : 26 free's of 657141197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_686] | 0 | - | 0.03 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9bd1fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1040] | 1 | True | 0.70 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b82960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016227754832832077 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 499.18 Core Time (ms) : 490.67 TIDL Subgraphs Processing Time (ms) : 490.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 178374025 bytes MEM: Free's : 26 free's of 178374025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1086] | 0 | - | 0.05 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d53990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.32 Core Time (ms) : 4.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_568] | 1 | True | 0.09 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d005c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015731836989402723 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.98 Core Time (ms) : 4.82 TIDL Subgraphs Processing Time (ms) : 4.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15352389 bytes MEM: Free's : 26 free's of 15352389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_209] | 1 | True | 5.71 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3d824a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0016549857838364691 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5300.23 Core Time (ms) : 5277.08 TIDL Subgraphs Processing Time (ms) : 5275.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 538866877 bytes MEM: Free's : 26 free's of 538866877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_582] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631ad070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_524] | 1 | True | 0.11 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c66120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00010433438426555145 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.07 Core Time (ms) : 4.91 TIDL Subgraphs Processing Time (ms) : 4.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21182957 bytes MEM: Free's : 26 free's of 21182957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1370] | 0 | - | 0.06 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630c5fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.90912827696359e-16 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.83 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_148] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631b1e60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.613074399805765e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1103] | 1 | True | 0.99 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631b79c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1861s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016200840685693413 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 706.89 Core Time (ms) : 673.41 TIDL Subgraphs Processing Time (ms) : 672.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 299727277 bytes MEM: Free's : 26 free's of 299727277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1313] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc007fc510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.187s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009052991411964063 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.67 Core Time (ms) : 1.57 TIDL Subgraphs Processing Time (ms) : 1.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14252261 bytes MEM: Free's : 26 free's of 14252261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_41] | 1 | True | 0.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d47e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002479131995772145 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.98 Core Time (ms) : 16.58 TIDL Subgraphs Processing Time (ms) : 16.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20525965 bytes MEM: Free's : 26 free's of 20525965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_267] | 1 | True | 0.09 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164df21a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013576704164650877 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.30 Core Time (ms) : 3.24 TIDL Subgraphs Processing Time (ms) : 3.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13506493 bytes MEM: Free's : 26 free's of 13506493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_602] | 0 | - | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008e7c70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.70 Core Time (ms) : 1.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1169] | 1 | True | 0.14 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164df1f60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015499108879251159 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.76 Core Time (ms) : 31.44 TIDL Subgraphs Processing Time (ms) : 31.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20158171 bytes MEM: Free's : 26 free's of 20158171 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_995] | 0 | - | 0.06 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c6b280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_320] | 0 | - | 0.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c6a190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_64] | 0 | - | 0.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d56ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 7.931753700220009e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_78] | 1 | True | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164ee0db0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015111123639486023 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 92.17 Core Time (ms) : 90.15 TIDL Subgraphs Processing Time (ms) : 90.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 56802877 bytes MEM: Free's : 26 free's of 56802877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1151] | 1 | True | 0.47 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d58d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2067s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000166435799752151 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 323.17 Core Time (ms) : 320.01 TIDL Subgraphs Processing Time (ms) : 319.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77368645 bytes MEM: Free's : 26 free's of 77368645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_703] | 1 | True | 12.55 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc005218b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016897600161115196 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11851.98 Core Time (ms) : 11807.77 TIDL Subgraphs Processing Time (ms) : 11804.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 997439529 bytes MEM: Free's : 26 free's of 997439529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_739] | 1 | True | 0.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164eecc30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5967s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014416333276276325 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.49 Core Time (ms) : 26.13 TIDL Subgraphs Processing Time (ms) : 26.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19294117 bytes MEM: Free's : 26 free's of 19294117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_898] | 0 | - | 0.13 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164b80680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.17 Core Time (ms) : 7.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1183] | 1 | True | 0.19 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e04990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007942496594994405 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 102.42 Core Time (ms) : 101.42 TIDL Subgraphs Processing Time (ms) : 101.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36587342 bytes MEM: Free's : 26 free's of 36587342 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_381] | 1 | True | 0.11 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d71fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014656403889609076 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.06 Core Time (ms) : 35.92 TIDL Subgraphs Processing Time (ms) : 35.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19565885 bytes MEM: Free's : 26 free's of 19565885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_210] | 1 | True | 0.33 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d596c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001574715803640056 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 213.55 Core Time (ms) : 211.97 TIDL Subgraphs Processing Time (ms) : 211.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38541355 bytes MEM: Free's : 26 free's of 38541355 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1371] | 1 | True | 0.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e040c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.987595274145564e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.95 Core Time (ms) : 16.82 TIDL Subgraphs Processing Time (ms) : 16.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21348533 bytes MEM: Free's : 26 free's of 21348533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1043] | 1 | True | 0.07 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630c80b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1198s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.012720989916744979 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.88 Core Time (ms) : 0.80 TIDL Subgraphs Processing Time (ms) : 0.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13917181 bytes MEM: Free's : 26 free's of 13917181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_950] | 1 | True | 0.13 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164eeeb00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001574476187496613 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.66 Core Time (ms) : 24.31 TIDL Subgraphs Processing Time (ms) : 24.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37347093 bytes MEM: Free's : 26 free's of 37347093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1328] | 0 | - | 0.04 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e777180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_424] | 1 | True | 0.12 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630c8340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0281568150863838 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.48 Core Time (ms) : 11.61 TIDL Subgraphs Processing Time (ms) : 11.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32180409 bytes MEM: Free's : 26 free's of 32180409 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_510] | 0 | - | 0.03 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164ef38a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_191] | 1 | True | 0.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630d1510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013111363007816025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.42 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 1.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13491133 bytes MEM: Free's : 26 free's of 13491133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_883] | 0 | - | 0.06 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143632344b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.342997485199942e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.58 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_382] | 0 | - | 0.03 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a429130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.23 Core Time (ms) : 1.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_854] | 0 | - | 0.05 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a429280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.54 Core Time (ms) : 1.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1143] | 1 | True | 0.13 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a92adc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014623698175015472 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 57.04 Core Time (ms) : 56.90 TIDL Subgraphs Processing Time (ms) : 56.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20067925 bytes MEM: Free's : 26 free's of 20067925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_676] | 1 | True | 0.45 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686823fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001575885903713586 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 358.10 Core Time (ms) : 356.33 TIDL Subgraphs Processing Time (ms) : 356.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51033589 bytes MEM: Free's : 26 free's of 51033589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_461] | 1 | True | 0.07 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a876b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015121632032036062 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.18 Core Time (ms) : 3.10 TIDL Subgraphs Processing Time (ms) : 3.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14585645 bytes MEM: Free's : 26 free's of 14585645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_484] | 1 | True | 0.14 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a9193e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015824660811469035 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.21 Core Time (ms) : 61.36 TIDL Subgraphs Processing Time (ms) : 61.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32058053 bytes MEM: Free's : 26 free's of 32058053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_575] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a91cb70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001460158638264735 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.82 Core Time (ms) : 4.44 TIDL Subgraphs Processing Time (ms) : 4.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20782117 bytes MEM: Free's : 26 free's of 20782117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_707] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a91cee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014563338129074084 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.32 Core Time (ms) : 17.13 TIDL Subgraphs Processing Time (ms) : 17.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23773269 bytes MEM: Free's : 26 free's of 23773269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_877] | 1 | True | 0.14 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b1b700 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.996533698205932e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.02 Core Time (ms) : 35.98 TIDL Subgraphs Processing Time (ms) : 35.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36070357 bytes MEM: Free's : 26 free's of 36070357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1123] | 1 | True | 1.04 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a922ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0017706681902331372 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 884.90 Core Time (ms) : 878.51 TIDL Subgraphs Processing Time (ms) : 878.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 162476081 bytes MEM: Free's : 26 free's of 162476081 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_804] | 1 | True | 0.13 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686bffa50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001860959898469327 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.10 Core Time (ms) : 36.02 TIDL Subgraphs Processing Time (ms) : 35.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37777045 bytes MEM: Free's : 26 free's of 37777045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_85] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b10d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014879472918494265 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.23 Core Time (ms) : 37.02 TIDL Subgraphs Processing Time (ms) : 36.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24404589 bytes MEM: Free's : 26 free's of 24404589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_469] | 1 | True | 0.36 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a83fb20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00037596908812846495 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 190.94 Core Time (ms) : 184.43 TIDL Subgraphs Processing Time (ms) : 184.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157475849 bytes MEM: Free's : 26 free's of 157475849 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_450] | 1 | True | 0.09 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb416e060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029880013560531302 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.56 Core Time (ms) : 12.26 TIDL Subgraphs Processing Time (ms) : 12.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20820725 bytes MEM: Free's : 26 free's of 20820725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_983] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4088030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_313] | 1 | True | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb408a410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002525439912962796 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.63 Core Time (ms) : 53.76 TIDL Subgraphs Processing Time (ms) : 53.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 148733109 bytes MEM: Free's : 26 free's of 148733109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_448] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4096b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_217] | 1 | True | 8.56 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3da2de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016802721112012546 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8001.18 Core Time (ms) : 7970.24 TIDL Subgraphs Processing Time (ms) : 7969.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 648622181 bytes MEM: Free's : 26 free's of 648622181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_974] | 1 | True | 0.61 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008ed060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015974550161071524 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 424.74 Core Time (ms) : 417.06 TIDL Subgraphs Processing Time (ms) : 416.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 193965901 bytes MEM: Free's : 26 free's of 193965901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_293] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008055e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1403s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03087044434919106 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.23 Core Time (ms) : 3.85 TIDL Subgraphs Processing Time (ms) : 3.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26353165 bytes MEM: Free's : 26 free's of 26353165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_654] | 0 | - | 0.02 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00965280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1161] | 1 | True | 0.08 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008fb000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011316352588449092 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.30 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12504021 bytes MEM: Free's : 26 free's of 12504021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_741] | 1 | True | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008fc440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012133454336722285 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.30 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12445925 bytes MEM: Free's : 26 free's of 12445925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1382] | 1 | True | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0080e750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014258653847180802 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.59 Core Time (ms) : 5.48 TIDL Subgraphs Processing Time (ms) : 5.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16988445 bytes MEM: Free's : 26 free's of 16988445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_548] | 1 | True | 0.14 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008f9190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014538483514846688 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.23 Core Time (ms) : 51.06 TIDL Subgraphs Processing Time (ms) : 51.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39402395 bytes MEM: Free's : 26 free's of 39402395 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_362] | 1 | True | 0.13 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00810430 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1227s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1228s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.014112532229104668 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.23 Core Time (ms) : 51.34 TIDL Subgraphs Processing Time (ms) : 51.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31893913 bytes MEM: Free's : 26 free's of 31893913 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1264] | 0 | - | 0.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008fc1a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2651219762362635e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.90 Core Time (ms) : 1.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_552] | 1 | True | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008fd310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015194938291076965 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.04 Core Time (ms) : 16.41 TIDL Subgraphs Processing Time (ms) : 16.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29526837 bytes MEM: Free's : 26 free's of 29526837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1419] | 0 | - | 0.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc005218b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.58 Core Time (ms) : 5.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_706] | 0 | - | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc005211c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7107078983293104e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.55 Core Time (ms) : 4.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_821] | 1 | True | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009058d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017116406212720354 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 119.35 Core Time (ms) : 113.64 TIDL Subgraphs Processing Time (ms) : 113.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 135704677 bytes MEM: Free's : 26 free's of 135704677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_668] | 1 | True | 1.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3da2150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016008239027564226 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 913.43 Core Time (ms) : 904.89 TIDL Subgraphs Processing Time (ms) : 904.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 201877973 bytes MEM: Free's : 26 free's of 201877973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1106] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00904e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.000809155665967e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_503] | 1 | True | 0.39 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00904ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017870823907546797 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 195.93 Core Time (ms) : 187.75 TIDL Subgraphs Processing Time (ms) : 187.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 176675097 bytes MEM: Free's : 26 free's of 176675097 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_518] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00905df0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2797872589551777e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_177] | 1 | True | 3.50 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00522490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017013235411319512 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3025.12 Core Time (ms) : 2997.60 TIDL Subgraphs Processing Time (ms) : 2996.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 652688485 bytes MEM: Free's : 26 free's of 652688485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1348] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb41aef10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1443] | 1 | True | 0.09 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4091370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2006s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015483903334845555 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.95 Core Time (ms) : 3.80 TIDL Subgraphs Processing Time (ms) : 3.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17132629 bytes MEM: Free's : 26 free's of 17132629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1055] | 1 | True | 0.09 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46b6c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00395562250439155 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.75 Core Time (ms) : 7.18 TIDL Subgraphs Processing Time (ms) : 7.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24840301 bytes MEM: Free's : 26 free's of 24840301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_857] | 1 | True | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46b6610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016192565086527614 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 93.09 Core Time (ms) : 91.89 TIDL Subgraphs Processing Time (ms) : 91.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37809301 bytes MEM: Free's : 26 free's of 37809301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1317] | 0 | - | 0.02 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45ce9c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1080] | 1 | True | 0.48 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46b9990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1222s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016145946336267652 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 311.23 Core Time (ms) : 304.25 TIDL Subgraphs Processing Time (ms) : 304.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 170629085 bytes MEM: Free's : 26 free's of 170629085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_129] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45d3480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6112s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00029086703759391474 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.64 Core Time (ms) : 19.53 TIDL Subgraphs Processing Time (ms) : 19.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21132553 bytes MEM: Free's : 26 free's of 21132553 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_722] | 0 | - | 0.06 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42d2d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7374280621231174e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.04 Core Time (ms) : 5.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_715] | 1 | True | 7.63 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42d4300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001684309042018566 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7309.02 Core Time (ms) : 7290.04 TIDL Subgraphs Processing Time (ms) : 7289.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 443104457 bytes MEM: Free's : 26 free's of 443104457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_10] | 1 | True | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0081e840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.239231880768711e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.05 Core Time (ms) : 1.86 TIDL Subgraphs Processing Time (ms) : 1.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21759637 bytes MEM: Free's : 26 free's of 21759637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_858] | 1 | True | 0.22 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0090ab20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016191247354406654 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 121.76 Core Time (ms) : 119.46 TIDL Subgraphs Processing Time (ms) : 119.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61119781 bytes MEM: Free's : 26 free's of 61119781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1434] | 1 | True | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00824ea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017044195113164582 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.95 Core Time (ms) : 14.71 TIDL Subgraphs Processing Time (ms) : 14.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40856557 bytes MEM: Free's : 26 free's of 40856557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_38] | 1 | True | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00823050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001776770250066712 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.24 Core Time (ms) : 3.14 TIDL Subgraphs Processing Time (ms) : 3.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14781693 bytes MEM: Free's : 26 free's of 14781693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1232] | 1 | True | 0.09 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46c6a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1902s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012490380934757607 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.30 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12429101 bytes MEM: Free's : 26 free's of 12429101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_709] | 1 | True | 0.08 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45e4630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014693603297734985 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.46 Core Time (ms) : 1.40 TIDL Subgraphs Processing Time (ms) : 1.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13586573 bytes MEM: Free's : 26 free's of 13586573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1401] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46c3cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015562636050985509 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.53 Core Time (ms) : 8.04 TIDL Subgraphs Processing Time (ms) : 8.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32419997 bytes MEM: Free's : 26 free's of 32419997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_223] | 1 | True | 0.44 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42daf00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1369s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001599228560270754 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 322.21 Core Time (ms) : 319.76 TIDL Subgraphs Processing Time (ms) : 319.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70027797 bytes MEM: Free's : 26 free's of 70027797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_90] | 1 | True | 0.13 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46cc020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1477s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014330112128151505 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.88 Core Time (ms) : 34.88 TIDL Subgraphs Processing Time (ms) : 34.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 49257413 bytes MEM: Free's : 26 free's of 49257413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_812] | 1 | True | 0.14 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46cce70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014163855225963074 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.67 Core Time (ms) : 26.95 TIDL Subgraphs Processing Time (ms) : 26.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30210117 bytes MEM: Free's : 26 free's of 30210117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_33] | 1 | True | 0.14 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46ced30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015518451192246164 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.61 Core Time (ms) : 33.37 TIDL Subgraphs Processing Time (ms) : 33.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44289296 bytes MEM: Free's : 26 free's of 44289296 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_117] | 1 | True | 0.17 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45e9870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005103860544206701 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.36 Core Time (ms) : 33.20 TIDL Subgraphs Processing Time (ms) : 33.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37801233 bytes MEM: Free's : 26 free's of 37801233 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_579] | 1 | True | 0.16 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45eb150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 9.168448789920716e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.06 Core Time (ms) : 31.68 TIDL Subgraphs Processing Time (ms) : 31.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62047013 bytes MEM: Free's : 26 free's of 62047013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_777] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45f0520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001412871962164028 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.10 Core Time (ms) : 10.99 TIDL Subgraphs Processing Time (ms) : 10.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17599125 bytes MEM: Free's : 26 free's of 17599125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1154] | 0 | - | 0.06 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45ed380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1024] | 1 | True | 0.11 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f471a4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.151s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015867192347274314 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.10 Core Time (ms) : 9.92 TIDL Subgraphs Processing Time (ms) : 9.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21321952 bytes MEM: Free's : 26 free's of 21321952 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1261] | 1 | True | 1.24 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42f5c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001596245933046798 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1106.46 Core Time (ms) : 1103.26 TIDL Subgraphs Processing Time (ms) : 1103.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 86923993 bytes MEM: Free's : 26 free's of 86923993 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1152] | 1 | True | 0.23 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42f6370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014963808411899994 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 126.92 Core Time (ms) : 125.99 TIDL Subgraphs Processing Time (ms) : 125.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34990645 bytes MEM: Free's : 26 free's of 34990645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_414] | 1 | True | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46de900 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016097777841040102 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 119.11 Core Time (ms) : 116.06 TIDL Subgraphs Processing Time (ms) : 116.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 82201221 bytes MEM: Free's : 26 free's of 82201221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_125] | 1 | True | 2.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46e08c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00020435485333165478 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1708.47 Core Time (ms) : 1685.15 TIDL Subgraphs Processing Time (ms) : 1684.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 538367493 bytes MEM: Free's : 26 free's of 538367493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1165] | 1 | True | 0.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f42f7c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001570143375258716 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.72 Core Time (ms) : 32.06 TIDL Subgraphs Processing Time (ms) : 32.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26135565 bytes MEM: Free's : 26 free's of 26135565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_198] | 1 | True | 0.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f45ffba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006080236275982545 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.42 Core Time (ms) : 17.34 TIDL Subgraphs Processing Time (ms) : 17.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19660529 bytes MEM: Free's : 26 free's of 19660529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_698] | 0 | - | 0.03 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e696740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 3.184187965631519e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.94 Core Time (ms) : 0.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1094] | 0 | - | 0.05 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6972c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.91 Core Time (ms) : 0.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_666] | 0 | - | 0.05 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e77e600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.525565065873445e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.83 Core Time (ms) : 1.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_933] | 1 | True | 0.28 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e77b780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001985374544650429 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 77.21 Core Time (ms) : 68.75 TIDL Subgraphs Processing Time (ms) : 68.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 203153245 bytes MEM: Free's : 26 free's of 203153245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_752] | 0 | - | 0.06 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d550a70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3365520670187322e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.71 Core Time (ms) : 3.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_951] | 1 | True | 0.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d468390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012197745415138645 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.51 Core Time (ms) : 5.41 TIDL Subgraphs Processing Time (ms) : 5.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20392493 bytes MEM: Free's : 26 free's of 20392493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_276] | 0 | - | 0.07 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d185170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3419159912330436e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.84 Core Time (ms) : 2.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_841] | 0 | - | 0.02 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d555a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_731] | 1 | True | 1.62 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d556310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2004s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001601871411743534 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1476.32 Core Time (ms) : 1472.01 TIDL Subgraphs Processing Time (ms) : 1471.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107054729 bytes MEM: Free's : 26 free's of 107054729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1333] | 1 | True | 0.07 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da61b4f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005513762549409212 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.77 Core Time (ms) : 2.65 TIDL Subgraphs Processing Time (ms) : 2.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15826165 bytes MEM: Free's : 26 free's of 15826165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_726] | 0 | - | 0.02 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da70b290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_363] | 1 | True | 0.07 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da61ea70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014036428038048584 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.23 Core Time (ms) : 2.17 TIDL Subgraphs Processing Time (ms) : 2.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14163181 bytes MEM: Free's : 26 free's of 14163181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_393] | 0 | - | 0.03 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da840aa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 3.018439649314682e-17 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.75 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_296] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc32fa20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016380596550722188 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.10 Core Time (ms) : 10.08 TIDL Subgraphs Processing Time (ms) : 10.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35837297 bytes MEM: Free's : 26 free's of 35837297 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_563] | 1 | True | 0.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2489c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014913436588169992 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.19 Core Time (ms) : 2.03 TIDL Subgraphs Processing Time (ms) : 1.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14348987 bytes MEM: Free's : 26 free's of 14348987 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_892] | 1 | True | 0.39 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d185de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1267s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016094247010197318 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 256.49 Core Time (ms) : 253.21 TIDL Subgraphs Processing Time (ms) : 253.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 82979221 bytes MEM: Free's : 26 free's of 82979221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_876] | 1 | True | 0.89 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbf924c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6093s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016097104826575965 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 669.49 Core Time (ms) : 658.76 TIDL Subgraphs Processing Time (ms) : 658.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 197920261 bytes MEM: Free's : 26 free's of 197920261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1083] | 1 | True | 0.20 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d561100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015746030865728005 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 105.69 Core Time (ms) : 103.90 TIDL Subgraphs Processing Time (ms) : 103.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52707552 bytes MEM: Free's : 26 free's of 52707552 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_547] | 1 | True | 0.23 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d55c710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016625233006739503 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 117.09 Core Time (ms) : 114.42 TIDL Subgraphs Processing Time (ms) : 114.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73495549 bytes MEM: Free's : 26 free's of 73495549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_68] | 0 | - | 0.03 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d567270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.5614975921130445e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.60 Core Time (ms) : 0.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_358] | 1 | True | 0.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d475fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.160s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013933801120530865 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.31 Core Time (ms) : 12.07 TIDL Subgraphs Processing Time (ms) : 12.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15786733 bytes MEM: Free's : 26 free's of 15786733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1047] | 1 | True | 0.46 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc339bc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0015155332798133295 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 318.22 Core Time (ms) : 313.06 TIDL Subgraphs Processing Time (ms) : 312.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 125990688 bytes MEM: Free's : 26 free's of 125990688 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_145] | 1 | True | 0.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d47bfd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.388899802488625e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 50.13 Core Time (ms) : 49.15 TIDL Subgraphs Processing Time (ms) : 49.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34958385 bytes MEM: Free's : 26 free's of 34958385 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_433] | 1 | True | 0.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d5638c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0009996682030968236 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.36 Core Time (ms) : 10.70 TIDL Subgraphs Processing Time (ms) : 10.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28299165 bytes MEM: Free's : 26 free's of 28299165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_915] | 1 | True | 1.20 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d56afa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001742424493563775 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 594.89 Core Time (ms) : 549.22 TIDL Subgraphs Processing Time (ms) : 546.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 816342069 bytes MEM: Free's : 26 free's of 816342069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1318] | 0 | - | 0.03 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aeab250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.12 Core Time (ms) : 1.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_936] | 0 | - | 0.02 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc24e760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_736] | 1 | True | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aea6240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.462645839064512e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 93.02 Core Time (ms) : 92.11 TIDL Subgraphs Processing Time (ms) : 92.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34446869 bytes MEM: Free's : 26 free's of 34446869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_465] | 0 | - | 0.06 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc339590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.05 Core Time (ms) : 2.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1462] | 1 | True | 0.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc251fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011439760911617906 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.27 Core Time (ms) : 5.12 TIDL Subgraphs Processing Time (ms) : 5.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16149353 bytes MEM: Free's : 26 free's of 16149353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1098] | 0 | - | 0.03 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aeab2e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.162952052028173e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.35 Core Time (ms) : 4.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1296] | 1 | True | 0.15 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af935c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1147s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017890746879653242 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.38 Core Time (ms) : 34.26 TIDL Subgraphs Processing Time (ms) : 34.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60667305 bytes MEM: Free's : 26 free's of 60667305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_815] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc258150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016997408562198876 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.04 Core Time (ms) : 15.00 TIDL Subgraphs Processing Time (ms) : 14.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34846641 bytes MEM: Free's : 26 free's of 34846641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_926] | 1 | True | 0.34 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1f7eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001641560820669925 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 227.40 Core Time (ms) : 225.37 TIDL Subgraphs Processing Time (ms) : 225.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54557925 bytes MEM: Free's : 26 free's of 54557925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_599] | 1 | True | 3.84 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af94a70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018140017017443253 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3284.01 Core Time (ms) : 3249.55 TIDL Subgraphs Processing Time (ms) : 3249.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 560022637 bytes MEM: Free's : 26 free's of 560022637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_292] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3740d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_437] | 1 | True | 0.11 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883e3260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016364378651590426 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.45 Core Time (ms) : 15.55 TIDL Subgraphs Processing Time (ms) : 15.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27532041 bytes MEM: Free's : 26 free's of 27532041 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_386] | 0 | - | 0.03 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884d2f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1022] | 0 | - | 0.04 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883e68d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.118252707701753e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_385] | 1 | True | 0.17 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3880fd970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0022789915959650804 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 80.34 Core Time (ms) : 79.41 TIDL Subgraphs Processing Time (ms) : 79.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29670549 bytes MEM: Free's : 26 free's of 29670549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1104] | 1 | True | 0.13 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb10f910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 9.023885400144871e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.40 Core Time (ms) : 24.05 TIDL Subgraphs Processing Time (ms) : 23.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29604917 bytes MEM: Free's : 26 free's of 29604917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_43] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2a7c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007933179338862664 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.84 Core Time (ms) : 3.71 TIDL Subgraphs Processing Time (ms) : 3.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14695177 bytes MEM: Free's : 26 free's of 14695177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1176] | 1 | True | 0.35 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbfe0e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001614376326420413 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 255.14 Core Time (ms) : 253.72 TIDL Subgraphs Processing Time (ms) : 253.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39041781 bytes MEM: Free's : 26 free's of 39041781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1478] | 0 | - | 0.06 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb10f820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_496] | 1 | True | 0.13 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884d2cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014819590698134598 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.77 Core Time (ms) : 28.04 TIDL Subgraphs Processing Time (ms) : 27.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53907701 bytes MEM: Free's : 26 free's of 53907701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_921] | 1 | True | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1fb740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015134654625740027 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 146.34 Core Time (ms) : 143.77 TIDL Subgraphs Processing Time (ms) : 143.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69977309 bytes MEM: Free's : 26 free's of 69977309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_156] | 0 | - | 0.02 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883ee000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.0639939734271585e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1287] | 1 | True | 0.07 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883ec5c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04251518301771378 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.94 Core Time (ms) : 0.87 TIDL Subgraphs Processing Time (ms) : 0.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14206597 bytes MEM: Free's : 26 free's of 14206597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_870] | 1 | True | 0.08 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d480fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016515553122896379 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.28 Core Time (ms) : 8.13 TIDL Subgraphs Processing Time (ms) : 8.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17483733 bytes MEM: Free's : 26 free's of 17483733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_286] | 0 | - | 0.02 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883f2b20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1096] | 1 | True | 0.08 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d388550520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014450962748768166 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.60 Core Time (ms) : 2.52 TIDL Subgraphs Processing Time (ms) : 2.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14293617 bytes MEM: Free's : 26 free's of 14293617 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_952] | 1 | True | 0.15 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d570660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1476s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000157429544185601 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.53 Core Time (ms) : 39.86 TIDL Subgraphs Processing Time (ms) : 39.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 49044273 bytes MEM: Free's : 26 free's of 49044273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_212] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc26bd30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_201] | 1 | True | 6.64 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bae98320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0007949566562309591 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5938.49 Core Time (ms) : 5893.46 TIDL Subgraphs Processing Time (ms) : 5891.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 833430693 bytes MEM: Free's : 26 free's of 833430693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_768] | 0 | - | 0.04 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc26a070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_623] | 1 | True | 0.17 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc25ebb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014685451703662697 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 90.83 Core Time (ms) : 90.58 TIDL Subgraphs Processing Time (ms) : 90.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24408557 bytes MEM: Free's : 26 free's of 24408557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_578] | 0 | - | 0.04 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d184b60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.8321262258284e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_328] | 0 | - | 0.03 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d489220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.94 Core Time (ms) : 0.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1483] | 0 | - | 0.02 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d4853d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_348] | 0 | - | 0.02 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d4852b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1070] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc264a30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1085] | 1 | True | 0.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d485520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014408467934071896 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.42 Core Time (ms) : 12.04 TIDL Subgraphs Processing Time (ms) : 12.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29116677 bytes MEM: Free's : 26 free's of 29116677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1447] | 1 | True | 0.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc34f7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002831421278090714 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.44 Core Time (ms) : 27.76 TIDL Subgraphs Processing Time (ms) : 27.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28173929 bytes MEM: Free's : 26 free's of 28173929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1130] | 0 | - | 0.04 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d48cf40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.76 Core Time (ms) : 7.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_454] | 1 | True | 0.08 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d4887b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0024961033773293535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.48 Core Time (ms) : 5.32 TIDL Subgraphs Processing Time (ms) : 5.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18113529 bytes MEM: Free's : 26 free's of 18113529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_158] | 1 | True | 1.45 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d1888e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016023218824147653 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1273.78 Core Time (ms) : 1268.81 TIDL Subgraphs Processing Time (ms) : 1268.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 134376985 bytes MEM: Free's : 26 free's of 134376985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_483] | 1 | True | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc357620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.64s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001525028685060845 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.28 Core Time (ms) : 66.64 TIDL Subgraphs Processing Time (ms) : 66.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28550053 bytes MEM: Free's : 26 free's of 28550053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_438] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc35a1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.08 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_517] | 1 | True | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc35c590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001598632138291371 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.97 Core Time (ms) : 34.44 TIDL Subgraphs Processing Time (ms) : 34.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71836913 bytes MEM: Free's : 26 free's of 71836913 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1188] | 1 | True | 0.38 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689ebb8b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0093783099823747 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 282.91 Core Time (ms) : 281.56 TIDL Subgraphs Processing Time (ms) : 281.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42996141 bytes MEM: Free's : 26 free's of 42996141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_848] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc35b140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.69 Core Time (ms) : 1.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_280] | 0 | - | 0.02 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbf72270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.6775566381922704e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.63 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_918] | 1 | True | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc35eb30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016089803536411661 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 153.72 Core Time (ms) : 151.91 TIDL Subgraphs Processing Time (ms) : 151.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54629237 bytes MEM: Free's : 26 free's of 54629237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_650] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8181bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.567145789145202e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_291] | 1 | True | 0.10 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece817dcd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017150760897823657 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.00 Core Time (ms) : 8.29 TIDL Subgraphs Processing Time (ms) : 8.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26763149 bytes MEM: Free's : 26 free's of 26763149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_998] | 1 | True | 0.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8095fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014553466005798056 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.60 Core Time (ms) : 5.45 TIDL Subgraphs Processing Time (ms) : 5.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17629581 bytes MEM: Free's : 26 free's of 17629581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_98] | 1 | True | 0.42 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d1e340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015244936403665616 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 262.87 Core Time (ms) : 257.35 TIDL Subgraphs Processing Time (ms) : 257.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 126873981 bytes MEM: Free's : 26 free's of 126873981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1204] | 1 | True | 0.63 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a218d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015446986230083126 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 503.49 Core Time (ms) : 501.37 TIDL Subgraphs Processing Time (ms) : 501.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62032414 bytes MEM: Free's : 26 free's of 62032414 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_834] | 0 | - | 0.02 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2744b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1308] | 1 | True | 0.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc35e490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001529812617104181 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.09 Core Time (ms) : 16.51 TIDL Subgraphs Processing Time (ms) : 16.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27833445 bytes MEM: Free's : 26 free's of 27833445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_76] | 0 | - | 0.05 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80983b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.872142767375911e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.35 Core Time (ms) : 8.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_459] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece809b1b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_769] | 1 | True | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8098f60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015281022805822784 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 110.89 Core Time (ms) : 110.15 TIDL Subgraphs Processing Time (ms) : 110.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30421953 bytes MEM: Free's : 26 free's of 30421953 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_453] | 1 | True | 0.16 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc360b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00026615751031634717 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.55 Core Time (ms) : 51.53 TIDL Subgraphs Processing Time (ms) : 51.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34533933 bytes MEM: Free's : 26 free's of 34533933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_399] | 1 | True | 0.15 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d576bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1281s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002043507024627871 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.36 Core Time (ms) : 30.66 TIDL Subgraphs Processing Time (ms) : 30.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69528305 bytes MEM: Free's : 26 free's of 69528305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_376] | 1 | True | 0.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3d5e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006890887256938448 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.43 Core Time (ms) : 3.32 TIDL Subgraphs Processing Time (ms) : 3.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14288653 bytes MEM: Free's : 26 free's of 14288653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_937] | 1 | True | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e77f50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.042766090698382636 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.08 Core Time (ms) : 5.62 TIDL Subgraphs Processing Time (ms) : 5.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25973437 bytes MEM: Free's : 26 free's of 25973437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1006] | 0 | - | 0.04 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc27ab20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_800] | 0 | - | 0.04 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c376f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1400] | 1 | True | 0.12 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d576fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014755688448546593 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.70 Core Time (ms) : 9.81 TIDL Subgraphs Processing Time (ms) : 9.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30937813 bytes MEM: Free's : 26 free's of 30937813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1156] | 1 | True | 0.09 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc27d180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.429124066130102e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.23 Core Time (ms) : 6.09 TIDL Subgraphs Processing Time (ms) : 6.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15188725 bytes MEM: Free's : 26 free's of 15188725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_258] | 0 | - | 0.04 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c417f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.22 Core Time (ms) : 4.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1397] | 0 | - | 0.05 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f64e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.42 Core Time (ms) : 1.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_60] | 0 | - | 0.04 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c3a2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.523178079355293e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_780] | 0 | - | 0.07 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d5790e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3515251683863383e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.33 Core Time (ms) : 18.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1421] | 0 | - | 0.02 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c3b710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_288] | 0 | - | 0.06 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2857c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.378723884647184e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.72 Core Time (ms) : 0.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_838] | 1 | True | 0.11 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e79ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001443420284849257 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.79 Core Time (ms) : 3.73 TIDL Subgraphs Processing Time (ms) : 3.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13929277 bytes MEM: Free's : 26 free's of 13929277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_303] | 1 | True | 0.23 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c3d2b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1477s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02119367998627889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 74.64 Core Time (ms) : 69.97 TIDL Subgraphs Processing Time (ms) : 69.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 113961077 bytes MEM: Free's : 26 free's of 113961077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_982] | 1 | True | 0.17 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc36a420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001508010319726725 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 77.42 Core Time (ms) : 76.39 TIDL Subgraphs Processing Time (ms) : 76.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31421381 bytes MEM: Free's : 26 free's of 31421381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1193] | 1 | True | 0.11 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d49e100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.247655200040795e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.83 Core Time (ms) : 2.80 TIDL Subgraphs Processing Time (ms) : 2.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13154549 bytes MEM: Free's : 26 free's of 13154549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_122] | 1 | True | 0.14 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a137440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004971625385109536 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.35 Core Time (ms) : 29.91 TIDL Subgraphs Processing Time (ms) : 29.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31746181 bytes MEM: Free's : 26 free's of 31746181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_388] | 1 | True | 0.51 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f6add0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016009346328492704 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 376.53 Core Time (ms) : 373.16 TIDL Subgraphs Processing Time (ms) : 373.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76969973 bytes MEM: Free's : 26 free's of 76969973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_239] | 1 | True | 0.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d494e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005130374789519372 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.32 Core Time (ms) : 5.23 TIDL Subgraphs Processing Time (ms) : 5.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14249045 bytes MEM: Free's : 26 free's of 14249045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1054] | 0 | - | 0.05 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2824b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.04371357246324e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.24 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_842] | 1 | True | 0.14 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c41480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1874s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.352582933062328e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.14 Core Time (ms) : 26.21 TIDL Subgraphs Processing Time (ms) : 26.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31021685 bytes MEM: Free's : 26 free's of 31021685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1058] | 0 | - | 0.05 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3e4280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.42 Core Time (ms) : 3.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1374] | 1 | True | 0.18 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbf81800 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015805876617087429 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 90.41 Core Time (ms) : 89.14 TIDL Subgraphs Processing Time (ms) : 89.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38100637 bytes MEM: Free's : 26 free's of 38100637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_957] | 1 | True | 0.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c42420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001648923952609275 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.62 Core Time (ms) : 18.28 TIDL Subgraphs Processing Time (ms) : 18.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39623437 bytes MEM: Free's : 26 free's of 39623437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_958] | 1 | True | 0.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc286a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015788341658115306 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.96 Core Time (ms) : 7.41 TIDL Subgraphs Processing Time (ms) : 7.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22634541 bytes MEM: Free's : 26 free's of 22634541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1004] | 1 | True | 0.13 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e7ea80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011838877877383803 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.73 Core Time (ms) : 18.24 TIDL Subgraphs Processing Time (ms) : 18.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38488849 bytes MEM: Free's : 26 free's of 38488849 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_149] | 1 | True | 0.52 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d31790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016605049838336555 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 407.11 Core Time (ms) : 403.90 TIDL Subgraphs Processing Time (ms) : 403.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70101757 bytes MEM: Free's : 26 free's of 70101757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_511] | 1 | True | 0.11 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f6ae90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014158976967829784 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.00 Core Time (ms) : 15.08 TIDL Subgraphs Processing Time (ms) : 15.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31665853 bytes MEM: Free's : 26 free's of 31665853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_973] | 1 | True | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc373410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015787780745358984 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 94.75 Core Time (ms) : 93.05 TIDL Subgraphs Processing Time (ms) : 92.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731501 bytes MEM: Free's : 26 free's of 46731501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_775] | 1 | True | 0.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af997d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014058570277749384 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.94 Core Time (ms) : 15.63 TIDL Subgraphs Processing Time (ms) : 15.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18995333 bytes MEM: Free's : 26 free's of 18995333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_923] | 1 | True | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f6edc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001528697625292853 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 200.95 Core Time (ms) : 198.48 TIDL Subgraphs Processing Time (ms) : 198.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70093309 bytes MEM: Free's : 26 free's of 70093309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1039] | 1 | True | 1.71 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af9e1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6073s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0017849389069104944 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1248.17 Core Time (ms) : 1220.52 TIDL Subgraphs Processing Time (ms) : 1219.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 529621237 bytes MEM: Free's : 26 free's of 529621237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1436] | 1 | True | 0.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc376b80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015797128218579228 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.60 Core Time (ms) : 29.30 TIDL Subgraphs Processing Time (ms) : 29.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38573917 bytes MEM: Free's : 26 free's of 38573917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_901] | 0 | - | 0.02 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc392980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_886] | 1 | True | 0.16 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237947650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014665999668228842 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 81.45 Core Time (ms) : 81.23 TIDL Subgraphs Processing Time (ms) : 81.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22613709 bytes MEM: Free's : 26 free's of 22613709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1144] | 1 | True | 0.18 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc379fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001496118067327356 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 90.52 Core Time (ms) : 89.64 TIDL Subgraphs Processing Time (ms) : 89.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32832949 bytes MEM: Free's : 26 free's of 32832949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_409] | 1 | True | 1.68 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f6e0e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017944062446639507 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1177.28 Core Time (ms) : 1146.77 TIDL Subgraphs Processing Time (ms) : 1145.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 660042933 bytes MEM: Free's : 26 free's of 660042933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1243] | 1 | True | 14.92 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237949b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017067526034741904 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14266.08 Core Time (ms) : 14226.13 TIDL Subgraphs Processing Time (ms) : 14223.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 977305961 bytes MEM: Free's : 26 free's of 977305961 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_910] | 1 | True | 0.18 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc37a7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001924066807274271 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.13 Core Time (ms) : 47.71 TIDL Subgraphs Processing Time (ms) : 47.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 84197119 bytes MEM: Free's : 26 free's of 84197119 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_351] | 1 | True | 0.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2923c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.059198745556407e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.10 Core Time (ms) : 2.03 TIDL Subgraphs Processing Time (ms) : 2.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14373557 bytes MEM: Free's : 26 free's of 14373557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_764] | 0 | - | 0.04 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3896b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2918575881022522e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.98 Core Time (ms) : 2.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_174] | 1 | True | 0.09 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc505450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001418102732248611 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.67 Core Time (ms) : 21.52 TIDL Subgraphs Processing Time (ms) : 21.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18575829 bytes MEM: Free's : 26 free's of 18575829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1109] | 1 | True | 0.07 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3b7990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.736736008897015e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.16 Core Time (ms) : 1.12 TIDL Subgraphs Processing Time (ms) : 1.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13332885 bytes MEM: Free's : 26 free's of 13332885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_36] | 0 | - | 0.02 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc299a30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_34] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc29a050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015863029138989606 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.43 Core Time (ms) : 10.75 TIDL Subgraphs Processing Time (ms) : 10.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32718377 bytes MEM: Free's : 26 free's of 32718377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1012] | 1 | True | 0.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b7f820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00019284699040857483 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 113.39 Core Time (ms) : 108.99 TIDL Subgraphs Processing Time (ms) : 108.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 90422408 bytes MEM: Free's : 26 free's of 90422408 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_850] | 0 | - | 0.02 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aeb2c80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1314] | 1 | True | 0.19 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afa6300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015515573909767174 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.53 Core Time (ms) : 65.06 TIDL Subgraphs Processing Time (ms) : 64.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61992541 bytes MEM: Free's : 26 free's of 61992541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_40] | 0 | - | 0.05 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b84180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_865] | 0 | - | 0.03 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9a9d410 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.7010003453237248e-17 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1207] | 1 | True | 5.37 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b98979a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016435370795761278 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5084.22 Core Time (ms) : 5069.62 TIDL Subgraphs Processing Time (ms) : 5069.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 375397173 bytes MEM: Free's : 26 free's of 375397173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_964] | 0 | - | 0.05 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afa2a30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.79 Core Time (ms) : 6.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1357] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e8d910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_207] | 1 | True | 0.12 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aeb4aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.023619229433462847 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.71 Core Time (ms) : 45.29 TIDL Subgraphs Processing Time (ms) : 45.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20479465 bytes MEM: Free's : 26 free's of 20479465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_130] | 1 | True | 0.14 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae49223f50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1224s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014442307344453523 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.31 Core Time (ms) : 54.61 TIDL Subgraphs Processing Time (ms) : 54.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31339045 bytes MEM: Free's : 26 free's of 31339045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1471] | 1 | True | 0.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e96020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001586150388094313 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 129.79 Core Time (ms) : 125.61 TIDL Subgraphs Processing Time (ms) : 125.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 82617565 bytes MEM: Free's : 26 free's of 82617565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1023] | 1 | True | 0.10 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e779970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001166627489714819 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.30 Core Time (ms) : 6.88 TIDL Subgraphs Processing Time (ms) : 6.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25981629 bytes MEM: Free's : 26 free's of 25981629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_321] | 1 | True | 0.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d0ecc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015701457799121115 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.47 Core Time (ms) : 6.30 TIDL Subgraphs Processing Time (ms) : 6.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15544153 bytes MEM: Free's : 26 free's of 15544153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1048] | 1 | True | 0.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e05740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9476s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008986575812407182 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.42 Core Time (ms) : 20.16 TIDL Subgraphs Processing Time (ms) : 20.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20973174 bytes MEM: Free's : 26 free's of 20973174 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1227] | 1 | True | 0.42 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e864f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015152303598909756 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 321.97 Core Time (ms) : 321.17 TIDL Subgraphs Processing Time (ms) : 321.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31475581 bytes MEM: Free's : 26 free's of 31475581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_885] | 1 | True | 0.26 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f50909b8580 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001575410041105452 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 158.11 Core Time (ms) : 156.49 TIDL Subgraphs Processing Time (ms) : 156.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36418741 bytes MEM: Free's : 26 free's of 36418741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_855] | 1 | True | 0.44 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164ef37c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015908370878881735 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 288.80 Core Time (ms) : 282.77 TIDL Subgraphs Processing Time (ms) : 282.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 100179941 bytes MEM: Free's : 26 free's of 100179941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_634] | 0 | - | 0.05 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e903e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.432571669351059e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1268] | 0 | - | 0.07 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614362dd25e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.864084338811353e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.16 Core Time (ms) : 7.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_988] | 1 | True | 0.17 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae490f8240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5976s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015777620415542712 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.30 Core Time (ms) : 66.57 TIDL Subgraphs Processing Time (ms) : 66.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22850165 bytes MEM: Free's : 26 free's of 22850165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_927] | 1 | True | 0.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d6a110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015671243573767886 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 122.42 Core Time (ms) : 121.77 TIDL Subgraphs Processing Time (ms) : 121.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33367509 bytes MEM: Free's : 26 free's of 33367509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_488] | 1 | True | 0.13 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630d1020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001523227816013561 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.62 Core Time (ms) : 33.44 TIDL Subgraphs Processing Time (ms) : 33.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21533421 bytes MEM: Free's : 26 free's of 21533421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_398] | 1 | True | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f7e520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4007s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002022954965137529 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 79.67 Core Time (ms) : 70.45 TIDL Subgraphs Processing Time (ms) : 70.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 140525737 bytes MEM: Free's : 26 free's of 140525737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_311] | 1 | True | 0.19 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e77f420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0021726581684395913 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.65 Core Time (ms) : 31.30 TIDL Subgraphs Processing Time (ms) : 31.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69700277 bytes MEM: Free's : 26 free's of 69700277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1332] | 0 | - | 0.04 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631bdb40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.13 Core Time (ms) : 2.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_648] | 1 | True | 0.16 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631b7f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015236933579220463 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.42 Core Time (ms) : 65.86 TIDL Subgraphs Processing Time (ms) : 65.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20527035 bytes MEM: Free's : 26 free's of 20527035 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_72] | 0 | - | 0.04 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164e0a7b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.6121873462020586e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.75 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1337] | 1 | True | 0.12 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c7d4d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2841s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014057045601423588 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.27 Core Time (ms) : 13.98 TIDL Subgraphs Processing Time (ms) : 13.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17620653 bytes MEM: Free's : 26 free's of 17620653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1326] | 0 | - | 0.06 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e7813a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.24 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1228] | 1 | True | 2.36 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48b9fb00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016075254985280094 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2209.07 Core Time (ms) : 2204.42 TIDL Subgraphs Processing Time (ms) : 2204.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 122326949 bytes MEM: Free's : 26 free's of 122326949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_16] | 0 | - | 0.06 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c81550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.02 Core Time (ms) : 2.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_965] | 1 | True | 0.15 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631c16a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014689652547382072 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.90 Core Time (ms) : 33.82 TIDL Subgraphs Processing Time (ms) : 33.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33644933 bytes MEM: Free's : 26 free's of 33644933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_79] | 1 | True | 0.13 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d722c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5643s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014837737216723187 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.76 Core Time (ms) : 23.38 TIDL Subgraphs Processing Time (ms) : 23.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24998397 bytes MEM: Free's : 26 free's of 24998397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1457] | 1 | True | 0.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631cbc30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015057843756636696 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.80 Core Time (ms) : 20.27 TIDL Subgraphs Processing Time (ms) : 20.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22841109 bytes MEM: Free's : 26 free's of 22841109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_113] | 1 | True | 0.39 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c815a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006449700344127761 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 243.04 Core Time (ms) : 238.42 TIDL Subgraphs Processing Time (ms) : 238.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 110785357 bytes MEM: Free's : 26 free's of 110785357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_17] | 1 | True | 1.07 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1ffa90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017863013143354465 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 623.82 Core Time (ms) : 598.65 TIDL Subgraphs Processing Time (ms) : 597.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 486436485 bytes MEM: Free's : 26 free's of 486436485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_567] | 1 | True | 0.13 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b1bea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015740708653818653 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.42 Core Time (ms) : 47.26 TIDL Subgraphs Processing Time (ms) : 47.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39523070 bytes MEM: Free's : 26 free's of 39523070 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_123] | 1 | True | 0.09 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090ccfac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009052080929773844 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.96 Core Time (ms) : 5.86 TIDL Subgraphs Processing Time (ms) : 5.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14470789 bytes MEM: Free's : 26 free's of 14470789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_942] | 1 | True | 0.09 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b1c660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5931s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5933s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014846793589609505 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.48 Core Time (ms) : 5.22 TIDL Subgraphs Processing Time (ms) : 5.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18130257 bytes MEM: Free's : 26 free's of 18130257 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_785] | 1 | True | 0.20 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b1e420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00019661705543786424 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.74 Core Time (ms) : 52.23 TIDL Subgraphs Processing Time (ms) : 52.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 109686041 bytes MEM: Free's : 26 free's of 109686041 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_500] | 1 | True | 0.12 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c0b9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00021896587476266413 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.62 Core Time (ms) : 22.26 TIDL Subgraphs Processing Time (ms) : 22.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37184197 bytes MEM: Free's : 26 free's of 37184197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_787] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b42b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.35314073177023303 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.82 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19516477 bytes MEM: Free's : 26 free's of 19516477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_208] | 0 | - | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686823f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.5529339856399074e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.61 Core Time (ms) : 5.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_514] | 0 | - | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c11710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.657169562237491e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.33 Core Time (ms) : 6.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_694] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b262f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.67 Core Time (ms) : 0.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_684] | 1 | True | 0.88 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686826720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016332782835507423 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 779.22 Core Time (ms) : 776.77 TIDL Subgraphs Processing Time (ms) : 776.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64704193 bytes MEM: Free's : 26 free's of 64704193 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_660] | 1 | True | 0.75 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb201ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015434385441691147 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 626.40 Core Time (ms) : 623.13 TIDL Subgraphs Processing Time (ms) : 623.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85256246 bytes MEM: Free's : 26 free's of 85256246 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1411] | 1 | True | 0.13 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a922ed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5875s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5877s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001463822635049048 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.21 Core Time (ms) : 32.19 TIDL Subgraphs Processing Time (ms) : 32.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34512525 bytes MEM: Free's : 26 free's of 34512525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1375] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a840110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001472232047931912 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.17 Core Time (ms) : 14.01 TIDL Subgraphs Processing Time (ms) : 13.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18170101 bytes MEM: Free's : 26 free's of 18170101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1202] | 0 | - | 0.03 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a92d530 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4669291427568663e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1168] | 1 | True | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48e98a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001425216758667569 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.30 Core Time (ms) : 16.12 TIDL Subgraphs Processing Time (ms) : 16.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17588677 bytes MEM: Free's : 26 free's of 17588677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1320] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b22500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015579069629923574 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.34 Core Time (ms) : 31.08 TIDL Subgraphs Processing Time (ms) : 31.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24402029 bytes MEM: Free's : 26 free's of 24402029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_340] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb203e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.70 Core Time (ms) : 1.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_884] | 1 | True | 0.33 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb11af10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014979617984221664 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 218.37 Core Time (ms) : 215.11 TIDL Subgraphs Processing Time (ms) : 215.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64413837 bytes MEM: Free's : 26 free's of 64413837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_867] | 1 | True | 0.16 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f84820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000153548416020866 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 73.78 Core Time (ms) : 73.47 TIDL Subgraphs Processing Time (ms) : 73.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25787349 bytes MEM: Free's : 26 free's of 25787349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1037] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b2c0b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014476265061921047 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.68 Core Time (ms) : 11.55 TIDL Subgraphs Processing Time (ms) : 11.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686880 bytes MEM: Free's : 26 free's of 18686880 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1126] | 0 | - | 0.09 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68682c130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3930087597980778e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.67 Core Time (ms) : 3.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_226] | 1 | True | 0.69 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f84e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015273591066286638 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 568.30 Core Time (ms) : 566.04 TIDL Subgraphs Processing Time (ms) : 565.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60758625 bytes MEM: Free's : 26 free's of 60758625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1217] | 1 | True | 0.09 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b32920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014173858576767856 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.48 Core Time (ms) : 5.38 TIDL Subgraphs Processing Time (ms) : 5.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14112785 bytes MEM: Free's : 26 free's of 14112785 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1474] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b32150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_28] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb206e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4532375198518113e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_193] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b31170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004941848942023563 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.01 Core Time (ms) : 7.86 TIDL Subgraphs Processing Time (ms) : 7.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15764501 bytes MEM: Free's : 26 free's of 15764501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_620] | 1 | True | 0.16 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb209280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001593794128378499 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.93 Core Time (ms) : 68.17 TIDL Subgraphs Processing Time (ms) : 68.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 49069061 bytes MEM: Free's : 26 free's of 49069061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1073] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b7f1a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015666846778382665 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.57 Core Time (ms) : 2.49 TIDL Subgraphs Processing Time (ms) : 2.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14542249 bytes MEM: Free's : 26 free's of 14542249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1002] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b34400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.32 Core Time (ms) : 8.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_75] | 1 | True | 0.07 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb11fc20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015980770112915488 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.36 Core Time (ms) : 1.31 TIDL Subgraphs Processing Time (ms) : 1.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13885125 bytes MEM: Free's : 26 free's of 13885125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1311] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b775f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_6] | 1 | True | 0.13 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c232e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001633076961826128 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.57 Core Time (ms) : 27.46 TIDL Subgraphs Processing Time (ms) : 27.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 56824609 bytes MEM: Free's : 26 free's of 56824609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_224] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb123350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.31 Core Time (ms) : 3.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_975] | 1 | True | 0.09 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb12ac80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016030544948699433 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.28 Core Time (ms) : 11.68 TIDL Subgraphs Processing Time (ms) : 11.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26228045 bytes MEM: Free's : 26 free's of 26228045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1293] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b2b530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00019166584566712665 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.94 Core Time (ms) : 2.72 TIDL Subgraphs Processing Time (ms) : 2.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23104373 bytes MEM: Free's : 26 free's of 23104373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1305] | 1 | True | 0.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb20f0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0004447408386272048 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.36 Core Time (ms) : 40.20 TIDL Subgraphs Processing Time (ms) : 40.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62598805 bytes MEM: Free's : 26 free's of 62598805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_260] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686ff4840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.032463749928517e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.74 Core Time (ms) : 0.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_697] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ea1ea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1555s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.027655258954699e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.97 Core Time (ms) : 6.81 TIDL Subgraphs Processing Time (ms) : 6.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15733073 bytes MEM: Free's : 26 free's of 15733073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1170] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686839410 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.0496856080312934e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.53 Core Time (ms) : 10.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1102] | 0 | - | 0.04 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb127380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3540237130985678e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_390] | 1 | True | 0.20 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68683a9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001503634290101707 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 98.90 Core Time (ms) : 98.03 TIDL Subgraphs Processing Time (ms) : 97.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29709533 bytes MEM: Free's : 26 free's of 29709533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1038] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb128540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1238] | 0 | - | 0.04 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f8f770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1330] | 1 | True | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb211d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004211115697904751 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 142.06 Core Time (ms) : 140.36 TIDL Subgraphs Processing Time (ms) : 140.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48264677 bytes MEM: Free's : 26 free's of 48264677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_671] | 1 | True | 0.35 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f8db80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014890257666962773 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 248.30 Core Time (ms) : 246.54 TIDL Subgraphs Processing Time (ms) : 246.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53313933 bytes MEM: Free's : 26 free's of 53313933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1386] | 1 | True | 2.61 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68683bcc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003704622671269616 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2275.74 Core Time (ms) : 2257.93 TIDL Subgraphs Processing Time (ms) : 2256.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 474624453 bytes MEM: Free's : 26 free's of 474624453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_762] | 0 | - | 0.04 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb3bc380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.1265319254129643e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.62 Core Time (ms) : 1.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_537] | 1 | True | 0.47 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb215560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016418888179051575 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 310.35 Core Time (ms) : 304.69 TIDL Subgraphs Processing Time (ms) : 304.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 135868081 bytes MEM: Free's : 26 free's of 135868081 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1020] | 1 | True | 0.71 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f8f780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017678569342449477 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 450.45 Core Time (ms) : 437.11 TIDL Subgraphs Processing Time (ms) : 436.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 255832019 bytes MEM: Free's : 26 free's of 255832019 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1336] | 0 | - | 0.02 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9a9b740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_346] | 1 | True | 0.12 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb130a40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015974705755488942 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.29 Core Time (ms) : 31.61 TIDL Subgraphs Processing Time (ms) : 31.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26253277 bytes MEM: Free's : 26 free's of 26253277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_244] | 0 | - | 0.06 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97a8040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.0321920365519e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.57 Core Time (ms) : 0.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1209] | 1 | True | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97a8680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015054277826678065 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 112.66 Core Time (ms) : 111.94 TIDL Subgraphs Processing Time (ms) : 111.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27937629 bytes MEM: Free's : 26 free's of 27937629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1376] | 1 | True | 0.09 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb12eb50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.285049399034971e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.83 Core Time (ms) : 4.63 TIDL Subgraphs Processing Time (ms) : 4.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15169317 bytes MEM: Free's : 26 free's of 15169317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1015] | 1 | True | 0.69 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb21ecb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016499543627810173 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 279.72 Core Time (ms) : 255.69 TIDL Subgraphs Processing Time (ms) : 254.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 485487669 bytes MEM: Free's : 26 free's of 485487669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_592] | 1 | True | 0.15 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b8ac40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014027381287889593 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.60 Core Time (ms) : 44.78 TIDL Subgraphs Processing Time (ms) : 44.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41431189 bytes MEM: Free's : 26 free's of 41431189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1404] | 1 | True | 0.40 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f90b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017151104746996446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 148.44 Core Time (ms) : 138.56 TIDL Subgraphs Processing Time (ms) : 137.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 215933909 bytes MEM: Free's : 26 free's of 215933909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_935] | 1 | True | 0.12 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9aa19b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.034521073339896444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.97 Core Time (ms) : 12.73 TIDL Subgraphs Processing Time (ms) : 12.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41443121 bytes MEM: Free's : 26 free's of 41443121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_298] | 1 | True | 0.12 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9aa4500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.133s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02682716453765639 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.13 Core Time (ms) : 12.26 TIDL Subgraphs Processing Time (ms) : 12.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33767117 bytes MEM: Free's : 26 free's of 33767117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_605] | 1 | True | 0.10 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9c45e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016129114600549945 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.67 Core Time (ms) : 14.35 TIDL Subgraphs Processing Time (ms) : 14.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18529225 bytes MEM: Free's : 26 free's of 18529225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1234] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ba7230 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.521646444521608e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_94] | 1 | True | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fd6b80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013889684212227215 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.56 Core Time (ms) : 21.37 TIDL Subgraphs Processing Time (ms) : 21.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20788032 bytes MEM: Free's : 26 free's of 20788032 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_728] | 1 | True | 1.82 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97a8030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001639107366037269 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1658.50 Core Time (ms) : 1652.86 TIDL Subgraphs Processing Time (ms) : 1652.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 141267165 bytes MEM: Free's : 26 free's of 141267165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1461] | 1 | True | 0.09 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb17e1d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014927388331329705 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.83 Core Time (ms) : 5.75 TIDL Subgraphs Processing Time (ms) : 5.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14638237 bytes MEM: Free's : 26 free's of 14638237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_318] | 1 | True | 0.09 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb17fbe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03713614019500455 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.81 Core Time (ms) : 1.70 TIDL Subgraphs Processing Time (ms) : 1.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14527869 bytes MEM: Free's : 26 free's of 14527869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1472] | 0 | - | 0.02 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb137e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_124] | 0 | - | 0.02 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb137fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_411] | 1 | True | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb221570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00027097003872340544 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 115.34 Core Time (ms) : 112.96 TIDL Subgraphs Processing Time (ms) : 112.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58757761 bytes MEM: Free's : 26 free's of 58757761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1441] | 1 | True | 0.10 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb23a000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6069s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6071s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004146752703201152 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.12 Core Time (ms) : 11.00 TIDL Subgraphs Processing Time (ms) : 10.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20284557 bytes MEM: Free's : 26 free's of 20284557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_844] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1406a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.82 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_417] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c2d340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.21 Core Time (ms) : 1.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_585] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b40130 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011716911662727973 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.45 Core Time (ms) : 1.38 TIDL Subgraphs Processing Time (ms) : 1.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13859509 bytes MEM: Free's : 26 free's of 13859509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_693] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b4d140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013648907938901058 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.61 Core Time (ms) : 1.56 TIDL Subgraphs Processing Time (ms) : 1.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13661549 bytes MEM: Free's : 26 free's of 13661549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1300] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b43440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1481] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b44850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_704] | 1 | True | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c38df0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015016077243669424 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 191.53 Core Time (ms) : 190.13 TIDL Subgraphs Processing Time (ms) : 190.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37093565 bytes MEM: Free's : 26 free's of 37093565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1392] | 0 | - | 0.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b49340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_700] | 1 | True | 0.16 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b47600 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1970s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015357481644990193 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 76.01 Core Time (ms) : 75.87 TIDL Subgraphs Processing Time (ms) : 75.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20573904 bytes MEM: Free's : 26 free's of 20573904 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_928] | 1 | True | 4.05 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97aa2f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017010640122479102 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3728.14 Core Time (ms) : 3710.48 TIDL Subgraphs Processing Time (ms) : 3709.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 426366157 bytes MEM: Free's : 26 free's of 426366157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_259] | 1 | True | 0.29 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686848750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015471721444951825 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 204.07 Core Time (ms) : 203.27 TIDL Subgraphs Processing Time (ms) : 203.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51338065 bytes MEM: Free's : 26 free's of 51338065 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_992] | 1 | True | 0.45 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c35360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1221s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015543227156874904 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 318.10 Core Time (ms) : 314.22 TIDL Subgraphs Processing Time (ms) : 314.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 102112981 bytes MEM: Free's : 26 free's of 102112981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_564] | 1 | True | 0.19 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c43aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015757312316826507 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.64 Core Time (ms) : 90.03 TIDL Subgraphs Processing Time (ms) : 89.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 49976133 bytes MEM: Free's : 26 free's of 49976133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1424] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b50420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1186s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000117760534798014 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.18 Core Time (ms) : 2.98 TIDL Subgraphs Processing Time (ms) : 2.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18473741 bytes MEM: Free's : 26 free's of 18473741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_702] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b5b1b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.23 Core Time (ms) : 7.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_301] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686cb8580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1062] | 0 | - | 0.05 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c3fd60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.8954806321220355e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.87 Core Time (ms) : 0.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_835] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b4be20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014428458245323747 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.96 Core Time (ms) : 1.86 TIDL Subgraphs Processing Time (ms) : 1.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14888765 bytes MEM: Free's : 26 free's of 14888765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_353] | 1 | True | 0.77 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c40830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015860555908860278 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 572.57 Core Time (ms) : 563.80 TIDL Subgraphs Processing Time (ms) : 563.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 215910933 bytes MEM: Free's : 26 free's of 215910933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1453] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686ba36e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1490s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001397578970171898 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.37 Core Time (ms) : 2.28 TIDL Subgraphs Processing Time (ms) : 2.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14788525 bytes MEM: Free's : 26 free's of 14788525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_463] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b5ae30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1430] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c47e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.03 Core Time (ms) : 1.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1271] | 1 | True | 2.52 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f6868d81a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002101424121783704 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2390.92 Core Time (ms) : 2386.53 TIDL Subgraphs Processing Time (ms) : 2386.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 119029664 bytes MEM: Free's : 26 free's of 119029664 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1142] | 0 | - | 0.03 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9aae150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_440] | 1 | True | 0.07 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9d60730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014646225940429127 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.47 Core Time (ms) : 5.37 TIDL Subgraphs Processing Time (ms) : 5.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19634141 bytes MEM: Free's : 26 free's of 19634141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_897] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68685c7f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.20 Core Time (ms) : 2.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1355] | 1 | True | 0.13 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68685ca20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015310379408053391 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.27 Core Time (ms) : 53.68 TIDL Subgraphs Processing Time (ms) : 53.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27148573 bytes MEM: Free's : 26 free's of 27148573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_667] | 1 | True | 0.16 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c4dbb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015902499106011436 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 83.15 Core Time (ms) : 82.63 TIDL Subgraphs Processing Time (ms) : 82.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23849005 bytes MEM: Free's : 26 free's of 23849005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_530] | 0 | - | 0.04 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c4d480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.898033080170023e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.72 Core Time (ms) : 0.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_161] | 1 | True | 0.09 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c53470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001452255363983107 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.37 Core Time (ms) : 14.71 TIDL Subgraphs Processing Time (ms) : 14.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25962765 bytes MEM: Free's : 26 free's of 25962765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1071] | 1 | True | 0.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c4f7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016160962310505147 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 101.53 Core Time (ms) : 97.61 TIDL Subgraphs Processing Time (ms) : 97.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77618181 bytes MEM: Free's : 26 free's of 77618181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1437] | 0 | - | 0.02 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c49810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_864] | 1 | True | 0.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c35d20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001501379051905612 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.17 Core Time (ms) : 14.93 TIDL Subgraphs Processing Time (ms) : 14.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15092857 bytes MEM: Free's : 26 free's of 15092857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_333] | 1 | True | 0.26 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c4f1a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010503334106684404 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 134.11 Core Time (ms) : 131.55 TIDL Subgraphs Processing Time (ms) : 131.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65189021 bytes MEM: Free's : 26 free's of 65189021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_914] | 1 | True | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d3a5d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001600619928112712 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.03 Core Time (ms) : 58.80 TIDL Subgraphs Processing Time (ms) : 58.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85188933 bytes MEM: Free's : 26 free's of 85188933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_327] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c5baa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.36 Core Time (ms) : 2.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_53] | 1 | True | 0.37 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c56080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00029284247060773185 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 224.95 Core Time (ms) : 219.76 TIDL Subgraphs Processing Time (ms) : 219.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 117360445 bytes MEM: Free's : 26 free's of 117360445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_765] | 1 | True | 0.14 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d40e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001548441584051232 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 58.14 Core Time (ms) : 57.69 TIDL Subgraphs Processing Time (ms) : 57.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26895237 bytes MEM: Free's : 26 free's of 26895237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_681] | 1 | True | 0.07 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c55590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1283s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001371447551396828 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.50 Core Time (ms) : 2.45 TIDL Subgraphs Processing Time (ms) : 2.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13867285 bytes MEM: Free's : 26 free's of 13867285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1445] | 1 | True | 0.11 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d40590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1556s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1558s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002856764018261006 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.67 Core Time (ms) : 20.97 TIDL Subgraphs Processing Time (ms) : 20.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26390621 bytes MEM: Free's : 26 free's of 26390621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1092] | 1 | True | 0.32 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c5d670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5811s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015376268519332357 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 175.65 Core Time (ms) : 172.34 TIDL Subgraphs Processing Time (ms) : 172.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 86255902 bytes MEM: Free's : 26 free's of 86255902 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_434] | 1 | True | 0.11 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d464d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0004845020516719255 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.26 Core Time (ms) : 17.23 TIDL Subgraphs Processing Time (ms) : 17.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29318313 bytes MEM: Free's : 26 free's of 29318313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1396] | 1 | True | 0.14 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d4a0a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018395202862955495 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.38 Core Time (ms) : 28.85 TIDL Subgraphs Processing Time (ms) : 28.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67486237 bytes MEM: Free's : 26 free's of 67486237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_862] | 1 | True | 0.17 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c57b10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1949s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000156042568187933 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.50 Core Time (ms) : 65.89 TIDL Subgraphs Processing Time (ms) : 65.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25944917 bytes MEM: Free's : 26 free's of 25944917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_695] | 1 | True | 0.49 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d4e0a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015341512733781714 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 385.95 Core Time (ms) : 383.97 TIDL Subgraphs Processing Time (ms) : 383.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64117205 bytes MEM: Free's : 26 free's of 64117205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_696] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b711c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.437964223123097e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.25 Core Time (ms) : 8.11 TIDL Subgraphs Processing Time (ms) : 8.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15666917 bytes MEM: Free's : 26 free's of 15666917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_471] | 1 | True | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b72f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000139666491649807 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.85 Core Time (ms) : 1.79 TIDL Subgraphs Processing Time (ms) : 1.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14318541 bytes MEM: Free's : 26 free's of 14318541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_801] | 1 | True | 0.10 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b74440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.026956111473787688 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.62 Core Time (ms) : 12.40 TIDL Subgraphs Processing Time (ms) : 12.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40913857 bytes MEM: Free's : 26 free's of 40913857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1310] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b76010 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1475] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b777d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014371584929064022 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.47 Core Time (ms) : 14.21 TIDL Subgraphs Processing Time (ms) : 14.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17427061 bytes MEM: Free's : 26 free's of 17427061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1372] | 1 | True | 0.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4096a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4025s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014289000430535594 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.50 Core Time (ms) : 43.12 TIDL Subgraphs Processing Time (ms) : 43.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20569005 bytes MEM: Free's : 26 free's of 20569005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_225] | 1 | True | 0.20 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c68550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.179s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.303389434623711e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 99.41 Core Time (ms) : 98.36 TIDL Subgraphs Processing Time (ms) : 98.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36174705 bytes MEM: Free's : 26 free's of 36174705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_588] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b789b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.879736167721958e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.04 Core Time (ms) : 1.95 TIDL Subgraphs Processing Time (ms) : 1.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14500277 bytes MEM: Free's : 26 free's of 14500277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1454] | 1 | True | 0.12 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb409e020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016256601462197784 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.72 Core Time (ms) : 31.30 TIDL Subgraphs Processing Time (ms) : 31.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35009261 bytes MEM: Free's : 26 free's of 35009261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1153] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b79de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.529248210276584e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.83 Core Time (ms) : 26.11 TIDL Subgraphs Processing Time (ms) : 26.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22524629 bytes MEM: Free's : 26 free's of 22524629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_869] | 1 | True | 0.34 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c32379669a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015675313849572976 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 242.30 Core Time (ms) : 240.82 TIDL Subgraphs Processing Time (ms) : 240.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47567481 bytes MEM: Free's : 26 free's of 47567481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_663] | 1 | True | 10.09 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f68687ae20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016291772103190397 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9373.51 Core Time (ms) : 9328.33 TIDL Subgraphs Processing Time (ms) : 9326.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1039393769 bytes MEM: Free's : 26 free's of 1039393769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1298] | 0 | - | 0.02 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c67750 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1203] | 1 | True | 0.14 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c6ce10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005585803491948808 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.44 Core Time (ms) : 61.86 TIDL Subgraphs Processing Time (ms) : 61.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27314798 bytes MEM: Free's : 26 free's of 27314798 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1393] | 1 | True | 0.18 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c6a400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010654935012135186 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 83.38 Core Time (ms) : 81.63 TIDL Subgraphs Processing Time (ms) : 81.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64560053 bytes MEM: Free's : 26 free's of 64560053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1327] | 1 | True | 0.52 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d568c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016467395958547415 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 331.24 Core Time (ms) : 322.22 TIDL Subgraphs Processing Time (ms) : 322.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 193921317 bytes MEM: Free's : 26 free's of 193921317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1210] | 0 | - | 0.02 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0055cd90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.928612607645914e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.87 Core Time (ms) : 0.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1013] | 1 | True | 0.38 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00917630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5975s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001604373507213469 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 196.03 Core Time (ms) : 188.63 TIDL Subgraphs Processing Time (ms) : 188.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 144492137 bytes MEM: Free's : 26 free's of 144492137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1158] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0056cac0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_187] | 1 | True | 0.16 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00916830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014844682601949065 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 80.87 Core Time (ms) : 80.29 TIDL Subgraphs Processing Time (ms) : 80.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31879712 bytes MEM: Free's : 26 free's of 31879712 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_607] | 1 | True | 0.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00832730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016981057778632923 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.55 Core Time (ms) : 33.98 TIDL Subgraphs Processing Time (ms) : 33.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27128118 bytes MEM: Free's : 26 free's of 27128118 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1390] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00979ca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_725] | 1 | True | 0.84 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00634fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1262s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1263s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017023314045099125 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 723.11 Core Time (ms) : 719.92 TIDL Subgraphs Processing Time (ms) : 719.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83956045 bytes MEM: Free's : 26 free's of 83956045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_422] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00833af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1831s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012649537178122399 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.13 Core Time (ms) : 2.98 TIDL Subgraphs Processing Time (ms) : 2.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18524401 bytes MEM: Free's : 26 free's of 18524401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1197] | 1 | True | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00575320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015136993677744204 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 209.41 Core Time (ms) : 207.73 TIDL Subgraphs Processing Time (ms) : 207.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53012549 bytes MEM: Free's : 26 free's of 53012549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_364] | 0 | - | 0.02 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008407c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_143] | 1 | True | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0083c690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005389563570277575 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.80 Core Time (ms) : 0.76 TIDL Subgraphs Processing Time (ms) : 0.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13217061 bytes MEM: Free's : 26 free's of 13217061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_871] | 0 | - | 0.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0053bfb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3513106656386334e-16 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1253] | 1 | True | 0.83 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0053d740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1198s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015301739557236051 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 719.61 Core Time (ms) : 717.07 TIDL Subgraphs Processing Time (ms) : 717.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73693333 bytes MEM: Free's : 26 free's of 73693333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1095] | 1 | True | 0.63 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0057de80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016837662485907353 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 449.43 Core Time (ms) : 441.79 TIDL Subgraphs Processing Time (ms) : 441.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 202015013 bytes MEM: Free's : 26 free's of 202015013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1273] | 1 | True | 0.78 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0053f360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015083701188840835 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 671.49 Core Time (ms) : 669.08 TIDL Subgraphs Processing Time (ms) : 669.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71008125 bytes MEM: Free's : 26 free's of 71008125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_447] | 1 | True | 0.16 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00931cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1288s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00541633177158237 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.00 Core Time (ms) : 59.02 TIDL Subgraphs Processing Time (ms) : 58.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58767709 bytes MEM: Free's : 26 free's of 58767709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_504] | 1 | True | 0.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00843900 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018129150353599885 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.15 Core Time (ms) : 23.18 TIDL Subgraphs Processing Time (ms) : 23.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37735793 bytes MEM: Free's : 26 free's of 37735793 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_489] | 1 | True | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009308f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003338993965129175 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.99 Core Time (ms) : 44.45 TIDL Subgraphs Processing Time (ms) : 44.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26030685 bytes MEM: Free's : 26 free's of 26030685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_118] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00844c80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5958s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00972273060842306 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.48 Core Time (ms) : 1.41 TIDL Subgraphs Processing Time (ms) : 1.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13517973 bytes MEM: Free's : 26 free's of 13517973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_102] | 1 | True | 0.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009380d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015587520036650944 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.36 Core Time (ms) : 26.78 TIDL Subgraphs Processing Time (ms) : 26.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32118009 bytes MEM: Free's : 26 free's of 32118009 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1388] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00bec1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.668838351187361e-16 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.03 Core Time (ms) : 1.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1274] | 0 | - | 0.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00939580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3367127989126477e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.06 Core Time (ms) : 1.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_214] | 1 | True | 0.52 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0055ebe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00277385963246187 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 429.97 Core Time (ms) : 428.63 TIDL Subgraphs Processing Time (ms) : 428.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 45117920 bytes MEM: Free's : 26 free's of 45117920 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_577] | 1 | True | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00596410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014814809138868806 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.91 Core Time (ms) : 39.05 TIDL Subgraphs Processing Time (ms) : 39.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33570589 bytes MEM: Free's : 26 free's of 33570589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_281] | 1 | True | 6.19 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0055e470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0006496738209576644 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5656.58 Core Time (ms) : 5623.33 TIDL Subgraphs Processing Time (ms) : 5622.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 785514501 bytes MEM: Free's : 26 free's of 785514501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1064] | 1 | True | 0.22 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46f2ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002819374759885993 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 110.83 Core Time (ms) : 108.16 TIDL Subgraphs Processing Time (ms) : 108.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70008461 bytes MEM: Free's : 26 free's of 70008461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_550] | 0 | - | 0.03 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46ec970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.929129259206772e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_134] | 1 | True | 0.45 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0055dd40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001773873977462163 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 316.44 Core Time (ms) : 314.20 TIDL Subgraphs Processing Time (ms) : 314.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60819873 bytes MEM: Free's : 26 free's of 60819873 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_114] | 1 | True | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0085b230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03186497243383573 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.50 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12751483 bytes MEM: Free's : 26 free's of 12751483 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1134] | 0 | - | 0.06 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008635b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1289] | 1 | True | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0085b670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.167s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3229s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001643512029514991 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.73 Core Time (ms) : 9.11 TIDL Subgraphs Processing Time (ms) : 9.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28422933 bytes MEM: Free's : 26 free's of 28422933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_781] | 1 | True | 0.15 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6c67c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001550945291660361 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.14 Core Time (ms) : 64.97 TIDL Subgraphs Processing Time (ms) : 64.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23018721 bytes MEM: Free's : 26 free's of 23018721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_791] | 1 | True | 0.09 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae800918920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.142s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2630s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2632s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001422180208332221 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.94 Core Time (ms) : 3.83 TIDL Subgraphs Processing Time (ms) : 3.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19995297 bytes MEM: Free's : 26 free's of 19995297 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_419] | 1 | True | 0.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008d9be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017336298379700248 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.02 Core Time (ms) : 7.93 TIDL Subgraphs Processing Time (ms) : 7.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33532253 bytes MEM: Free's : 26 free's of 33532253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_996] | 1 | True | 0.84 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e42fdb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001574691096804091 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 685.51 Core Time (ms) : 679.36 TIDL Subgraphs Processing Time (ms) : 679.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 147645713 bytes MEM: Free's : 26 free's of 147645713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1361] | 1 | True | 0.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008db550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014480343759562926 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.26 Core Time (ms) : 25.81 TIDL Subgraphs Processing Time (ms) : 25.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27428437 bytes MEM: Free's : 26 free's of 27428437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_24] | 0 | - | 0.04 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e698850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3404960569712554e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1331] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e69aab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001398043306365659 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.10 Core Time (ms) : 10.01 TIDL Subgraphs Processing Time (ms) : 9.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18585905 bytes MEM: Free's : 26 free's of 18585905 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1467] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e69a150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.013830027091714145 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.75 Core Time (ms) : 2.65 TIDL Subgraphs Processing Time (ms) : 2.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14248561 bytes MEM: Free's : 26 free's of 14248561 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_991] | 0 | - | 0.05 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da22d350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.92 Core Time (ms) : 1.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1201] | 1 | True | 0.13 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da626090 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2678s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.860063881267024e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.76 Core Time (ms) : 25.65 TIDL Subgraphs Processing Time (ms) : 25.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21357557 bytes MEM: Free's : 26 free's of 21357557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_890] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e69cad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.60s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.710451397971582e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.51 Core Time (ms) : 5.37 TIDL Subgraphs Processing Time (ms) : 5.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15729317 bytes MEM: Free's : 26 free's of 15729317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_903] | 1 | True | 0.11 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e69ebc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015120554886560868 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.92 Core Time (ms) : 20.79 TIDL Subgraphs Processing Time (ms) : 20.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18561677 bytes MEM: Free's : 26 free's of 18561677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_907] | 0 | - | 0.03 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da749cd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1010] | 0 | - | 0.02 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da628d80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_265] | 1 | True | 6.96 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da351d90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0025800778270719774 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6464.84 Core Time (ms) : 6433.63 TIDL Subgraphs Processing Time (ms) : 6432.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 632447253 bytes MEM: Free's : 26 free's of 632447253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_555] | 1 | True | 0.95 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7773f990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015910990207133576 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 684.01 Core Time (ms) : 671.05 TIDL Subgraphs Processing Time (ms) : 670.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 312182353 bytes MEM: Free's : 26 free's of 312182353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1001] | 1 | True | 0.10 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77656c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5975s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018931305206852872 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.33 Core Time (ms) : 8.69 TIDL Subgraphs Processing Time (ms) : 8.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27449481 bytes MEM: Free's : 26 free's of 27449481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_796] | 1 | True | 0.28 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda777423c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018034116279086668 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 105.39 Core Time (ms) : 98.20 TIDL Subgraphs Processing Time (ms) : 98.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157490021 bytes MEM: Free's : 26 free's of 157490021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_633] | 1 | True | 0.17 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7774cd00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1139s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013161831543418631 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 83.92 Core Time (ms) : 82.99 TIDL Subgraphs Processing Time (ms) : 82.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36736971 bytes MEM: Free's : 26 free's of 36736971 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1163] | 1 | True | 0.22 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77a1f290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015431449047655397 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 135.04 Core Time (ms) : 134.17 TIDL Subgraphs Processing Time (ms) : 134.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35821877 bytes MEM: Free's : 26 free's of 35821877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_761] | 1 | True | 0.11 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda776623a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1396s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001451164441004121 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.32 Core Time (ms) : 30.97 TIDL Subgraphs Processing Time (ms) : 30.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27681501 bytes MEM: Free's : 26 free's of 27681501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1394] | 1 | True | 0.75 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda773e8f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0037433252967533095 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 637.61 Core Time (ms) : 634.91 TIDL Subgraphs Processing Time (ms) : 634.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 79389105 bytes MEM: Free's : 26 free's of 79389105 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_341] | 1 | True | 0.66 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884ddd50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0014694198216887175 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 471.67 Core Time (ms) : 463.61 TIDL Subgraphs Processing Time (ms) : 463.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 205208541 bytes MEM: Free's : 26 free's of 205208541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_544] | 1 | True | 0.17 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77750d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015728396545481595 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.71 Core Time (ms) : 68.95 TIDL Subgraphs Processing Time (ms) : 68.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 49992133 bytes MEM: Free's : 26 free's of 49992133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1312] | 1 | True | 0.07 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda777c1050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005691978249986323 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.33 Core Time (ms) : 1.26 TIDL Subgraphs Processing Time (ms) : 1.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14322577 bytes MEM: Free's : 26 free's of 14322577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_136] | 0 | - | 0.03 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77669c70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2270720068681435e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.40 Core Time (ms) : 1.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1000] | 1 | True | 0.19 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77752e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017336625751380373 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 57.58 Core Time (ms) : 53.54 TIDL Subgraphs Processing Time (ms) : 53.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 112898273 bytes MEM: Free's : 26 free's of 112898273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1150] | 0 | - | 0.03 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77668160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.114397094544504e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_846] | 1 | True | 0.10 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7766a6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.810594054150774e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.65 Core Time (ms) : 13.96 TIDL Subgraphs Processing Time (ms) : 13.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26979893 bytes MEM: Free's : 26 free's of 26979893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_580] | 1 | True | 0.08 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3883f6760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.986511849651697e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.76 Core Time (ms) : 2.60 TIDL Subgraphs Processing Time (ms) : 2.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16191633 bytes MEM: Free's : 26 free's of 16191633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_967] | 0 | - | 0.03 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77760140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.88 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_84] | 0 | - | 0.02 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7766c310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 9.881133839403595e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_443] | 0 | - | 0.02 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7766ce00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_245] | 1 | True | 0.74 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3880f5b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1217s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016179518623450018 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 609.55 Core Time (ms) : 604.89 TIDL Subgraphs Processing Time (ms) : 604.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 114811425 bytes MEM: Free's : 26 free's of 114811425 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_738] | 0 | - | 0.04 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda777847b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.761718556549101e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_352] | 1 | True | 0.18 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7775a910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001463042270957622 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 93.17 Core Time (ms) : 92.07 TIDL Subgraphs Processing Time (ms) : 92.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39230069 bytes MEM: Free's : 26 free's of 39230069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_154] | 1 | True | 1.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda773788e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001541858024980221 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 920.05 Core Time (ms) : 914.20 TIDL Subgraphs Processing Time (ms) : 914.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 145860221 bytes MEM: Free's : 26 free's of 145860221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1414] | 1 | True | 0.33 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3880fcc40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015692039886013043 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 229.78 Core Time (ms) : 228.11 TIDL Subgraphs Processing Time (ms) : 228.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51747997 bytes MEM: Free's : 26 free's of 51747997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_664] | 1 | True | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3880fd290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001462454962680053 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 163.93 Core Time (ms) : 162.67 TIDL Subgraphs Processing Time (ms) : 162.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39272917 bytes MEM: Free's : 26 free's of 39272917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1146] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80a7430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1140] | 1 | True | 2.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7e1e410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5981s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016382607368252446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1840.99 Core Time (ms) : 1827.54 TIDL Subgraphs Processing Time (ms) : 1827.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 268905633 bytes MEM: Free's : 26 free's of 268905633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_61] | 1 | True | 1.03 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884ea6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002295922035371038 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 743.59 Core Time (ms) : 729.75 TIDL Subgraphs Processing Time (ms) : 729.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 314689201 bytes MEM: Free's : 26 free's of 314689201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_774] | 0 | - | 0.05 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77763c20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.33 Core Time (ms) : 3.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_8] | 0 | - | 0.04 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7775ff40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.77 Core Time (ms) : 3.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1003] | 1 | True | 0.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77675460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1271s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04257606397352162 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.65 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19757965 bytes MEM: Free's : 26 free's of 19757965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1285] | 1 | True | 0.76 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda773789a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1188s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016279508307426223 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 629.87 Core Time (ms) : 625.96 TIDL Subgraphs Processing Time (ms) : 625.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89560693 bytes MEM: Free's : 26 free's of 89560693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1417] | 0 | - | 0.03 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a485600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.22 Core Time (ms) : 1.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1280] | 0 | - | 0.03 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a138090 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_732] | 1 | True | 0.08 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d498f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.700881612652193e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.00 Core Time (ms) : 7.90 TIDL Subgraphs Processing Time (ms) : 7.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14835541 bytes MEM: Free's : 26 free's of 14835541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_345] | 1 | True | 0.08 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a13abf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.686502768109326e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.83 Core Time (ms) : 5.63 TIDL Subgraphs Processing Time (ms) : 5.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17444293 bytes MEM: Free's : 26 free's of 17444293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1263] | 1 | True | 0.30 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a225d00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00364343045681211 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 204.80 Core Time (ms) : 203.24 TIDL Subgraphs Processing Time (ms) : 203.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37453557 bytes MEM: Free's : 26 free's of 37453557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_677] | 1 | True | 0.25 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a225450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015467697477390498 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 158.76 Core Time (ms) : 157.30 TIDL Subgraphs Processing Time (ms) : 157.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52026773 bytes MEM: Free's : 26 free's of 52026773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_219] | 1 | True | 0.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77678de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017158434526578568 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.86 Core Time (ms) : 1.79 TIDL Subgraphs Processing Time (ms) : 1.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13527501 bytes MEM: Free's : 26 free's of 13527501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_534] | 0 | - | 0.03 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7767b580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_264] | 0 | - | 0.07 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3880ff740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3536637705944467e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.49 Core Time (ms) : 6.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_170] | 1 | True | 0.37 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689eba490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014966025525612117 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 243.48 Core Time (ms) : 241.56 TIDL Subgraphs Processing Time (ms) : 241.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52230309 bytes MEM: Free's : 26 free's of 52230309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1034] | 0 | - | 0.03 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6c46b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_839] | 0 | - | 0.02 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da62c880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_790] | 1 | True | 0.09 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a13fac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04094131804048636 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.61 Core Time (ms) : 4.16 TIDL Subgraphs Processing Time (ms) : 4.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27889125 bytes MEM: Free's : 26 free's of 27889125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_924] | 1 | True | 0.30 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a22fef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015223147752084314 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 211.48 Core Time (ms) : 209.68 TIDL Subgraphs Processing Time (ms) : 209.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55820485 bytes MEM: Free's : 26 free's of 55820485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_379] | 1 | True | 0.13 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a14fa50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.535690847160708e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.13 Core Time (ms) : 40.08 TIDL Subgraphs Processing Time (ms) : 40.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34489349 bytes MEM: Free's : 26 free's of 34489349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1265] | 1 | True | 0.80 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e5b170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015419829299741174 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 695.99 Core Time (ms) : 693.36 TIDL Subgraphs Processing Time (ms) : 693.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68196573 bytes MEM: Free's : 26 free's of 68196573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_498] | 0 | - | 0.05 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece818afb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4639124132549814e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1160] | 1 | True | 0.07 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc394160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014919353516799712 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.45 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12573349 bytes MEM: Free's : 26 free's of 12573349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_304] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80a2d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000151157869984571 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.44 Core Time (ms) : 8.13 TIDL Subgraphs Processing Time (ms) : 8.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25645061 bytes MEM: Free's : 26 free's of 25645061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1451] | 1 | True | 0.07 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2a09e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012771651034961147 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.70 Core Time (ms) : 1.63 TIDL Subgraphs Processing Time (ms) : 1.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14281769 bytes MEM: Free's : 26 free's of 14281769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_989] | 1 | True | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7da5d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015062079260114083 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 88.08 Core Time (ms) : 87.37 TIDL Subgraphs Processing Time (ms) : 87.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30435665 bytes MEM: Free's : 26 free's of 30435665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1173] | 1 | True | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc38bd00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001486568342629496 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 115.46 Core Time (ms) : 114.43 TIDL Subgraphs Processing Time (ms) : 114.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51827982 bytes MEM: Free's : 26 free's of 51827982 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_712] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece819a4e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014248272626283615 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.41 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12509269 bytes MEM: Free's : 26 free's of 12509269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_392] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7da4480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.1614217472034265e-18 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.27 Core Time (ms) : 1.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_344] | 1 | True | 0.16 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3928c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001626679968758184 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 73.47 Core Time (ms) : 72.82 TIDL Subgraphs Processing Time (ms) : 72.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27984557 bytes MEM: Free's : 26 free's of 27984557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1018] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80a95d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.19 Core Time (ms) : 3.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_15] | 1 | True | 0.14 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8194170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015858278154714126 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.55 Core Time (ms) : 34.81 TIDL Subgraphs Processing Time (ms) : 34.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53641420 bytes MEM: Free's : 26 free's of 53641420 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_705] | 1 | True | 0.22 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc399ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001536632628571921 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 126.47 Core Time (ms) : 125.52 TIDL Subgraphs Processing Time (ms) : 125.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50302245 bytes MEM: Free's : 26 free's of 50302245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1459] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80aca40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00699174766714187 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.27 Core Time (ms) : 6.12 TIDL Subgraphs Processing Time (ms) : 6.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17985169 bytes MEM: Free's : 26 free's of 17985169 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_332] | 1 | True | 0.51 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81a39e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017878990258197764 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 331.69 Core Time (ms) : 325.63 TIDL Subgraphs Processing Time (ms) : 325.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 142517133 bytes MEM: Free's : 26 free's of 142517133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1225] | 1 | True | 0.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e5aac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000156040959122471 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 182.83 Core Time (ms) : 182.10 TIDL Subgraphs Processing Time (ms) : 182.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29901229 bytes MEM: Free's : 26 free's of 29901229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_529] | 1 | True | 0.09 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2ab2c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4389556711928858 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.70 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19525453 bytes MEM: Free's : 26 free's of 19525453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_39] | 1 | True | 0.07 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2aa870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014865863558143695 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.44 Core Time (ms) : 1.38 TIDL Subgraphs Processing Time (ms) : 1.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14174105 bytes MEM: Free's : 26 free's of 14174105 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1011] | 1 | True | 1.65 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a2365d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1220s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017474606165829922 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1094.01 Core Time (ms) : 1060.67 TIDL Subgraphs Processing Time (ms) : 1060.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 581035083 bytes MEM: Free's : 26 free's of 581035083 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_811] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80afb40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014051513759571487 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.63 Core Time (ms) : 6.54 TIDL Subgraphs Processing Time (ms) : 6.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18909805 bytes MEM: Free's : 26 free's of 18909805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1254] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece819fea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1220] | 1 | True | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece819ccf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1305s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015278144315972224 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 183.43 Core Time (ms) : 182.98 TIDL Subgraphs Processing Time (ms) : 182.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33220533 bytes MEM: Free's : 26 free's of 33220533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_192] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece819e2d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.5243465352869443e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.87 Core Time (ms) : 0.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_356] | 0 | - | 0.05 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81a2c30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.58 Core Time (ms) : 3.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1359] | 1 | True | 0.72 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7dfb580 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001585390792384967 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 527.95 Core Time (ms) : 520.53 TIDL Subgraphs Processing Time (ms) : 520.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 162314181 bytes MEM: Free's : 26 free's of 162314181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1440] | 1 | True | 0.09 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164efc0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016121848375794893 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.99 Core Time (ms) : 13.78 TIDL Subgraphs Processing Time (ms) : 13.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23859189 bytes MEM: Free's : 26 free's of 23859189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_913] | 1 | True | 1.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164f039a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016651723213051775 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 610.90 Core Time (ms) : 579.54 TIDL Subgraphs Processing Time (ms) : 578.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 655925309 bytes MEM: Free's : 26 free's of 655925309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_646] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630e7100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7353079070255817e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_19] | 1 | True | 0.16 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631ca5f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016479759030582367 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.81 Core Time (ms) : 41.86 TIDL Subgraphs Processing Time (ms) : 41.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52403207 bytes MEM: Free's : 26 free's of 52403207 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_759] | 1 | True | 0.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81a7ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014132511070431605 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.21 Core Time (ms) : 13.94 TIDL Subgraphs Processing Time (ms) : 13.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18736293 bytes MEM: Free's : 26 free's of 18736293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_335] | 1 | True | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631e29f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007810765236487969 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.74 Core Time (ms) : 12.60 TIDL Subgraphs Processing Time (ms) : 12.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19468917 bytes MEM: Free's : 26 free's of 19468917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_478] | 1 | True | 0.11 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80bfe40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015133298285418547 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.68 Core Time (ms) : 28.95 TIDL Subgraphs Processing Time (ms) : 28.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27536749 bytes MEM: Free's : 26 free's of 27536749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_182] | 1 | True | 0.21 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614362e21d90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1227s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1229s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008265038894213287 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 133.82 Core Time (ms) : 133.55 TIDL Subgraphs Processing Time (ms) : 133.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23952256 bytes MEM: Free's : 26 free's of 23952256 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_613] | 1 | True | 0.97 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689ecaa70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016580977566069225 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 804.53 Core Time (ms) : 798.37 TIDL Subgraphs Processing Time (ms) : 798.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 149632789 bytes MEM: Free's : 26 free's of 149632789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_370] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80c18a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1090] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80c1d70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_23] | 1 | True | 0.11 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f509101ec50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001372013525629429 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.63 Core Time (ms) : 23.82 TIDL Subgraphs Processing Time (ms) : 23.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34270816 bytes MEM: Free's : 26 free's of 34270816 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_543] | 1 | True | 1.93 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81b5e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016868910312913855 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1386.17 Core Time (ms) : 1348.67 TIDL Subgraphs Processing Time (ms) : 1347.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 567675701 bytes MEM: Free's : 26 free's of 567675701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_893] | 1 | True | 0.14 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630e8110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015175069400513754 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.67 Core Time (ms) : 47.01 TIDL Subgraphs Processing Time (ms) : 46.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25457965 bytes MEM: Free's : 26 free's of 25457965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_797] | 1 | True | 0.09 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c895c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001532232679936383 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.40 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 1.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20087745 bytes MEM: Free's : 26 free's of 20087745 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_347] | 1 | True | 0.08 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c8c2b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.834626639764175e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.12 Core Time (ms) : 3.98 TIDL Subgraphs Processing Time (ms) : 3.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15596981 bytes MEM: Free's : 26 free's of 15596981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_326] | 1 | True | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614363248f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014571696163420445 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.53 Core Time (ms) : 1.42 TIDL Subgraphs Processing Time (ms) : 1.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14376589 bytes MEM: Free's : 26 free's of 14376589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1270] | 0 | - | 0.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c86fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_866] | 1 | True | 0.29 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c98c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.197436363455049e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 146.09 Core Time (ms) : 141.48 TIDL Subgraphs Processing Time (ms) : 141.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 106317285 bytes MEM: Free's : 26 free's of 106317285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_932] | 0 | - | 0.03 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630e95e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_74] | 1 | True | 0.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164f42370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001533386410756647 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.89 Core Time (ms) : 18.77 TIDL Subgraphs Processing Time (ms) : 18.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20395344 bytes MEM: Free's : 26 free's of 20395344 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_200] | 0 | - | 0.04 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d7f500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.51 Core Time (ms) : 7.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_252] | 0 | - | 0.02 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d83320 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_150] | 1 | True | 0.08 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090d818e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012937914683391612 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.27 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12417301 bytes MEM: Free's : 26 free's of 12417301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1281] | 1 | True | 0.17 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c909e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1209s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015717630296450193 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.17 Core Time (ms) : 90.54 TIDL Subgraphs Processing Time (ms) : 90.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29191285 bytes MEM: Free's : 26 free's of 29191285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_361] | 0 | - | 0.03 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a14e4d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1132] | 1 | True | 0.53 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a2386e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5959s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001587734315237173 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 407.17 Core Time (ms) : 402.75 TIDL Subgraphs Processing Time (ms) : 402.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89191437 bytes MEM: Free's : 26 free's of 89191437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1190] | 0 | - | 0.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090ca04b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 3.368441496060804e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.51 Core Time (ms) : 7.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_930] | 0 | - | 0.06 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090996170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.68 Core Time (ms) : 3.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_542] | 0 | - | 0.02 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a842ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1286] | 0 | - | 0.02 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a934520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1455] | 1 | True | 0.07 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a843260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1195s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1197s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001414621678181326 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.23 Core Time (ms) : 4.10 TIDL Subgraphs Processing Time (ms) : 4.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17491573 bytes MEM: Free's : 26 free's of 17491573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1365] | 0 | - | 0.04 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a932370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_713] | 1 | True | 0.08 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a896cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001514527960206006 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.81 Core Time (ms) : 7.72 TIDL Subgraphs Processing Time (ms) : 7.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14480918 bytes MEM: Free's : 26 free's of 14480918 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1406] | 1 | True | 1.13 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a23f7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1403s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001893420720616162 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 553.58 Core Time (ms) : 517.74 TIDL Subgraphs Processing Time (ms) : 516.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 791179125 bytes MEM: Free's : 26 free's of 791179125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1122] | 0 | - | 0.04 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a936aa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.331723583822886e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.80 Core Time (ms) : 0.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_442] | 1 | True | 0.31 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a84a850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014684114496302955 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 98.05 Core Time (ms) : 87.50 TIDL Subgraphs Processing Time (ms) : 87.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 167453677 bytes MEM: Free's : 26 free's of 167453677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_979] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a850550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1871s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001568505414492139 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.52 Core Time (ms) : 9.43 TIDL Subgraphs Processing Time (ms) : 9.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20633661 bytes MEM: Free's : 26 free's of 20633661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1350] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80c60b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015252320029665744 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.32 Core Time (ms) : 7.16 TIDL Subgraphs Processing Time (ms) : 7.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17819093 bytes MEM: Free's : 26 free's of 17819093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1291] | 1 | True | 0.10 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a84bbe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1872s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018110364375129885 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.45 Core Time (ms) : 10.88 TIDL Subgraphs Processing Time (ms) : 10.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29830469 bytes MEM: Free's : 26 free's of 29830469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_917] | 1 | True | 0.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81b0b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014826157389190392 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.99 Core Time (ms) : 12.87 TIDL Subgraphs Processing Time (ms) : 12.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19501793 bytes MEM: Free's : 26 free's of 19501793 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1347] | 1 | True | 0.25 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a855030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.532576828483103e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 113.21 Core Time (ms) : 107.32 TIDL Subgraphs Processing Time (ms) : 107.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107118757 bytes MEM: Free's : 26 free's of 107118757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_649] | 1 | True | 0.38 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7dcb500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015086487890994703 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 248.38 Core Time (ms) : 244.96 TIDL Subgraphs Processing Time (ms) : 244.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 84485477 bytes MEM: Free's : 26 free's of 84485477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1112] | 1 | True | 0.79 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a554fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016121367958682933 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 630.29 Core Time (ms) : 624.80 TIDL Subgraphs Processing Time (ms) : 624.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 136733565 bytes MEM: Free's : 26 free's of 136733565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1482] | 1 | True | 0.61 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7dcbc40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0037153676313987677 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 473.49 Core Time (ms) : 469.29 TIDL Subgraphs Processing Time (ms) : 469.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 114496321 bytes MEM: Free's : 26 free's of 114496321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_851] | 1 | True | 0.08 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a155650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.801791452926687e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.07 Core Time (ms) : 3.88 TIDL Subgraphs Processing Time (ms) : 3.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17124181 bytes MEM: Free's : 26 free's of 17124181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_165] | 1 | True | 5.02 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e5b750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016528236749053425 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4603.16 Core Time (ms) : 4579.23 TIDL Subgraphs Processing Time (ms) : 4578.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 563639429 bytes MEM: Free's : 26 free's of 563639429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1425] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80cd7b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016158109927881222 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.42 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 1.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14017197 bytes MEM: Free's : 26 free's of 14017197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_222] | 1 | True | 0.43 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a5542e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001542264434175417 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 350.40 Core Time (ms) : 349.59 TIDL Subgraphs Processing Time (ms) : 349.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32303533 bytes MEM: Free's : 26 free's of 32303533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1187] | 1 | True | 0.13 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80d2e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01014626982002885 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.09 Core Time (ms) : 44.37 TIDL Subgraphs Processing Time (ms) : 44.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32743953 bytes MEM: Free's : 26 free's of 32743953 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1282] | 0 | - | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7dced30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3440036884547342e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.86 Core Time (ms) : 11.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1028] | 1 | True | 0.11 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81bb3e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001594182966137847 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.56 Core Time (ms) : 25.50 TIDL Subgraphs Processing Time (ms) : 25.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39372729 bytes MEM: Free's : 26 free's of 39372729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1422] | 0 | - | 0.05 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81bdff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_176] | 0 | - | 0.03 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a554f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.6930688139641443e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.46 Core Time (ms) : 2.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1114] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80d6410 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_147] | 1 | True | 0.50 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a5d3760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1270s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015778747704421432 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 385.81 Core Time (ms) : 382.13 TIDL Subgraphs Processing Time (ms) : 382.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85973189 bytes MEM: Free's : 26 free's of 85973189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_446] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8120240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014046502040477495 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.17 Core Time (ms) : 3.07 TIDL Subgraphs Processing Time (ms) : 3.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14829385 bytes MEM: Free's : 26 free's of 14829385 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_946] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80d8820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.19 Core Time (ms) : 4.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1241] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece812a360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014363379496758953 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.42 Core Time (ms) : 8.33 TIDL Subgraphs Processing Time (ms) : 8.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14557609 bytes MEM: Free's : 26 free's of 14557609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_151] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81cc820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013779952912054932 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.24 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12414133 bytes MEM: Free's : 26 free's of 12414133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_163] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80d6160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004616863986742055 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.72 Core Time (ms) : 5.63 TIDL Subgraphs Processing Time (ms) : 5.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14891494 bytes MEM: Free's : 26 free's of 14891494 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_526] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81cb010 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.6215986698708228e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.65 Core Time (ms) : 0.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1284] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81c9e50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3530584556166746e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.60 Core Time (ms) : 2.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1200] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80e8680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.026903381458887772 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.74 Core Time (ms) : 1.68 TIDL Subgraphs Processing Time (ms) : 1.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13643765 bytes MEM: Free's : 26 free's of 13643765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_523] | 1 | True | 0.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a855f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 9.21786523986329e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.22 Core Time (ms) : 8.61 TIDL Subgraphs Processing Time (ms) : 8.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30858573 bytes MEM: Free's : 26 free's of 30858573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1335] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80e3ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.012883021859176906 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.50 Core Time (ms) : 2.39 TIDL Subgraphs Processing Time (ms) : 2.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14892133 bytes MEM: Free's : 26 free's of 14892133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_477] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80e44c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.63s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014212679562794478 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.90 Core Time (ms) : 6.75 TIDL Subgraphs Processing Time (ms) : 6.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17651293 bytes MEM: Free's : 26 free's of 17651293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_859] | 1 | True | 0.11 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81d2da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014469312033537702 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.25 Core Time (ms) : 27.84 TIDL Subgraphs Processing Time (ms) : 27.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20762677 bytes MEM: Free's : 26 free's of 20762677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_825] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f964d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014565008331337846 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.64 Core Time (ms) : 10.22 TIDL Subgraphs Processing Time (ms) : 10.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27664357 bytes MEM: Free's : 26 free's of 27664357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_295] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80f28b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_573] | 1 | True | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f97ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001648505174613884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 126.59 Core Time (ms) : 123.84 TIDL Subgraphs Processing Time (ms) : 123.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75040085 bytes MEM: Free's : 26 free's of 75040085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1381] | 1 | True | 0.16 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81c2d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004136548963807827 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 81.73 Core Time (ms) : 81.36 TIDL Subgraphs Processing Time (ms) : 81.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22765969 bytes MEM: Free's : 26 free's of 22765969 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1315] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80ed570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.310123303048857e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.61 Core Time (ms) : 4.48 TIDL Subgraphs Processing Time (ms) : 4.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21380645 bytes MEM: Free's : 26 free's of 21380645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_141] | 1 | True | 1.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48befe10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001450804513390978 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 907.58 Core Time (ms) : 898.97 TIDL Subgraphs Processing Time (ms) : 898.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 200501461 bytes MEM: Free's : 26 free's of 200501461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1100] | 1 | True | 0.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80ec770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.757732655806827e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.28 Core Time (ms) : 3.16 TIDL Subgraphs Processing Time (ms) : 3.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14926005 bytes MEM: Free's : 26 free's of 14926005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1079] | 1 | True | 0.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81dd760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001582730135322143 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 97.86 Core Time (ms) : 95.32 TIDL Subgraphs Processing Time (ms) : 95.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62142587 bytes MEM: Free's : 26 free's of 62142587 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_611] | 1 | True | 1.05 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bae84a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016639143876683471 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 873.66 Core Time (ms) : 866.35 TIDL Subgraphs Processing Time (ms) : 866.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 191406253 bytes MEM: Free's : 26 free's of 191406253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_571] | 1 | True | 0.48 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81dcf30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1551s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015725861437168836 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 326.65 Core Time (ms) : 321.28 TIDL Subgraphs Processing Time (ms) : 321.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 133009985 bytes MEM: Free's : 26 free's of 133009985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1059] | 1 | True | 0.14 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81dc4b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002817491598767851 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.76 Core Time (ms) : 51.87 TIDL Subgraphs Processing Time (ms) : 51.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34533933 bytes MEM: Free's : 26 free's of 34533933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_823] | 1 | True | 0.16 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81ddbe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015528156622482775 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.30 Core Time (ms) : 59.75 TIDL Subgraphs Processing Time (ms) : 59.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48234981 bytes MEM: Free's : 26 free's of 48234981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1235] | 1 | True | 2.44 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48bb4540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1242s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015878191300416325 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2248.41 Core Time (ms) : 2239.88 TIDL Subgraphs Processing Time (ms) : 2239.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 216245749 bytes MEM: Free's : 26 free's of 216245749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_360] | 1 | True | 1.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7df45c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016526426248200096 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 798.28 Core Time (ms) : 788.81 TIDL Subgraphs Processing Time (ms) : 788.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 242412901 bytes MEM: Free's : 26 free's of 242412901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_32] | 0 | - | 0.04 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb22a740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4728338046664799e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1269] | 1 | True | 0.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bae851d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000157052492416755 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 216.62 Core Time (ms) : 215.85 TIDL Subgraphs Processing Time (ms) : 215.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50708533 bytes MEM: Free's : 26 free's of 50708533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_756] | 0 | - | 0.06 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095baf46520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4066018798578027e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.82 Core Time (ms) : 5.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_740] | 1 | True | 0.08 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb1479e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.711154402387849e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.49 Core Time (ms) : 6.39 TIDL Subgraphs Processing Time (ms) : 6.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14574021 bytes MEM: Free's : 26 free's of 14574021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_827] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb238b20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.76 Core Time (ms) : 0.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1065] | 1 | True | 0.07 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb193fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01114610790006204 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.22 Core Time (ms) : 2.14 TIDL Subgraphs Processing Time (ms) : 2.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14466777 bytes MEM: Free's : 26 free's of 14466777 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_468] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80f9a80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_562] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81e5070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.501070216707711e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_314] | 1 | True | 0.12 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81e3210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0005193086786441802 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.73 Core Time (ms) : 24.49 TIDL Subgraphs Processing Time (ms) : 24.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42330549 bytes MEM: Free's : 26 free's of 42330549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_776] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7df9f70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.933501312490119e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.37 Core Time (ms) : 1.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_431] | 1 | True | 0.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80fce70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03145070601357497 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.17 Core Time (ms) : 4.69 TIDL Subgraphs Processing Time (ms) : 4.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22879485 bytes MEM: Free's : 26 free's of 22879485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1186] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece80fefb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_674] | 0 | - | 0.04 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece7dfd940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4663061268067023e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.95 Core Time (ms) : 1.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_278] | 0 | - | 0.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81eb940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1479] | 1 | True | 0.22 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81003a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008972436781828188 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 112.93 Core Time (ms) : 110.49 TIDL Subgraphs Processing Time (ms) : 110.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75840201 bytes MEM: Free's : 26 free's of 75840201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1128] | 1 | True | 0.12 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81094a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009636797537426203 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.51 Core Time (ms) : 29.41 TIDL Subgraphs Processing Time (ms) : 29.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36108005 bytes MEM: Free's : 26 free's of 36108005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1213] | 1 | True | 0.11 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a243730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.63s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014742898954949384 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.59 Core Time (ms) : 34.18 TIDL Subgraphs Processing Time (ms) : 34.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26808981 bytes MEM: Free's : 26 free's of 26808981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_211] | 1 | True | 0.08 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1a7bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060044622710285 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.44 Core Time (ms) : 6.34 TIDL Subgraphs Processing Time (ms) : 6.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14728525 bytes MEM: Free's : 26 free's of 14728525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_115] | 1 | True | 0.07 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a24bc50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001201427965703679 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.30 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12475389 bytes MEM: Free's : 26 free's of 12475389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_968] | 1 | True | 0.11 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a15fed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001551692024770097 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.04 Core Time (ms) : 19.85 TIDL Subgraphs Processing Time (ms) : 19.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38709777 bytes MEM: Free's : 26 free's of 38709777 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1369] | 1 | True | 0.09 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1622f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015287052304617199 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.19 Core Time (ms) : 10.95 TIDL Subgraphs Processing Time (ms) : 10.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17888701 bytes MEM: Free's : 26 free's of 17888701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1099] | 1 | True | 0.33 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fa7d20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001586725885644471 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 173.12 Core Time (ms) : 169.04 TIDL Subgraphs Processing Time (ms) : 168.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107837845 bytes MEM: Free's : 26 free's of 107837845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_93] | 1 | True | 0.28 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fa3500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015310153837203074 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 131.05 Core Time (ms) : 126.92 TIDL Subgraphs Processing Time (ms) : 126.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 109228261 bytes MEM: Free's : 26 free's of 109228261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_847] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48eb9bc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.023169305885340316 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.41 Core Time (ms) : 1.34 TIDL Subgraphs Processing Time (ms) : 1.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14065669 bytes MEM: Free's : 26 free's of 14065669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1091] | 1 | True | 3.37 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48bbe790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016552261505576427 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2673.00 Core Time (ms) : 2629.33 TIDL Subgraphs Processing Time (ms) : 2627.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1039214057 bytes MEM: Free's : 26 free's of 1039214057 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_959] | 0 | - | 0.04 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9ccbae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_350] | 1 | True | 0.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9b9c0f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014963253589770384 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.77 Core Time (ms) : 40.10 TIDL Subgraphs Processing Time (ms) : 40.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29623517 bytes MEM: Free's : 26 free's of 29623517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1275] | 1 | True | 0.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9ba0b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003079686339952443 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 204.63 Core Time (ms) : 203.67 TIDL Subgraphs Processing Time (ms) : 203.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38264373 bytes MEM: Free's : 26 free's of 38264373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_799] | 1 | True | 0.07 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9ab61d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001530252577820502 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.54 Core Time (ms) : 3.44 TIDL Subgraphs Processing Time (ms) : 3.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19218477 bytes MEM: Free's : 26 free's of 19218477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1195] | 1 | True | 7.82 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97c7d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016843842119556145 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7317.77 Core Time (ms) : 7287.28 TIDL Subgraphs Processing Time (ms) : 7286.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 744778997 bytes MEM: Free's : 26 free's of 744778997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_558] | 0 | - | 0.05 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fafa00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.853493460578078e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.60 Core Time (ms) : 1.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_403] | 1 | True | 0.16 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48faa070 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0006761629529548252 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.67 Core Time (ms) : 42.63 TIDL Subgraphs Processing Time (ms) : 42.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 82964085 bytes MEM: Free's : 26 free's of 82964085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_228] | 0 | - | 0.02 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ec70e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_188] | 0 | - | 0.04 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ec69c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.6806357074563255e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_779] | 1 | True | 1.88 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48bc69b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016169691891509014 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1691.88 Core Time (ms) : 1684.46 TIDL Subgraphs Processing Time (ms) : 1684.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 181765889 bytes MEM: Free's : 26 free's of 181765889 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_976] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb409cf80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1402] | 0 | - | 0.03 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb41899d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.74 Core Time (ms) : 0.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1380] | 1 | True | 0.13 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40a36f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015166658613416457 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.02 Core Time (ms) : 52.92 TIDL Subgraphs Processing Time (ms) : 52.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22121921 bytes MEM: Free's : 26 free's of 22121921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_961] | 0 | - | 0.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb40a2140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_595] | 1 | True | 0.23 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d5dd20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015708376799245942 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 123.08 Core Time (ms) : 120.44 TIDL Subgraphs Processing Time (ms) : 120.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71595293 bytes MEM: Free's : 26 free's of 71595293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_96] | 0 | - | 0.02 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ec6820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 9.093603645920013e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_160] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fb7400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4129278910473048e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_819] | 1 | True | 0.07 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ec7a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001382607859071014 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.12 Core Time (ms) : 1.07 TIDL Subgraphs Processing Time (ms) : 1.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13929021 bytes MEM: Free's : 26 free's of 13929021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1329] | 1 | True | 0.15 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fb3c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006328138953926991 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.32 Core Time (ms) : 65.53 TIDL Subgraphs Processing Time (ms) : 65.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32552593 bytes MEM: Free's : 26 free's of 32552593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_7] | 1 | True | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c749f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013545243655384393 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.39 Core Time (ms) : 1.34 TIDL Subgraphs Processing Time (ms) : 1.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20026469 bytes MEM: Free's : 26 free's of 20026469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_513] | 1 | True | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c76650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015162429535058088 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.90 Core Time (ms) : 2.77 TIDL Subgraphs Processing Time (ms) : 2.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22855861 bytes MEM: Free's : 26 free's of 22855861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_591] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ecc0d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.730469224552654e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.47 Core Time (ms) : 10.72 TIDL Subgraphs Processing Time (ms) : 10.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28762993 bytes MEM: Free's : 26 free's of 28762993 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_436] | 1 | True | 0.11 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d67950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016606022831079222 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.07 Core Time (ms) : 24.90 TIDL Subgraphs Processing Time (ms) : 24.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40293617 bytes MEM: Free's : 26 free's of 40293617 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_439] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ecd350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1308s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015273339836094444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.43 Core Time (ms) : 6.17 TIDL Subgraphs Processing Time (ms) : 6.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24459933 bytes MEM: Free's : 26 free's of 24459933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_284] | 0 | - | 0.06 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237985940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.90 Core Time (ms) : 1.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_653] | 1 | True | 0.08 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48f1df20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014255011710418198 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.92 Core Time (ms) : 4.81 TIDL Subgraphs Processing Time (ms) : 4.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14676774 bytes MEM: Free's : 26 free's of 14676774 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1378] | 1 | True | 0.18 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c32379fd930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015050284105671494 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 101.51 Core Time (ms) : 100.58 TIDL Subgraphs Processing Time (ms) : 100.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34295669 bytes MEM: Free's : 26 free's of 34295669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_342] | 1 | True | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c7d9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5976s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006003727005510859 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.80 Core Time (ms) : 1.66 TIDL Subgraphs Processing Time (ms) : 1.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14441685 bytes MEM: Free's : 26 free's of 14441685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1044] | 1 | True | 0.18 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d6b1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1511s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016799227641533151 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 88.50 Core Time (ms) : 86.58 TIDL Subgraphs Processing Time (ms) : 86.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63809333 bytes MEM: Free's : 26 free's of 63809333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_767] | 1 | True | 7.88 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237985fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016869615267052043 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7504.15 Core Time (ms) : 7482.81 TIDL Subgraphs Processing Time (ms) : 7481.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 527539973 bytes MEM: Free's : 26 free's of 527539973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_947] | 1 | True | 0.08 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9aba500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015742511173587315 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.43 Core Time (ms) : 3.29 TIDL Subgraphs Processing Time (ms) : 3.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18038941 bytes MEM: Free's : 26 free's of 18038941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_395] | 1 | True | 0.12 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97fdd70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0016622461049537738 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.14 Core Time (ms) : 39.92 TIDL Subgraphs Processing Time (ms) : 39.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24135533 bytes MEM: Free's : 26 free's of 24135533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_669] | 1 | True | 0.10 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9c1e710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014573159234793613 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.58 Core Time (ms) : 30.23 TIDL Subgraphs Processing Time (ms) : 30.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29916893 bytes MEM: Free's : 26 free's of 29916893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_290] | 1 | True | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c84870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018035747107117168 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.77 Core Time (ms) : 1.61 TIDL Subgraphs Processing Time (ms) : 1.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16480477 bytes MEM: Free's : 26 free's of 16480477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_922] | 1 | True | 0.13 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d719a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.137s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015279580582011786 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.31 Core Time (ms) : 19.03 TIDL Subgraphs Processing Time (ms) : 18.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28378597 bytes MEM: Free's : 26 free's of 28378597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_73] | 1 | True | 0.33 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c6ede0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1103s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016922967373878017 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 206.74 Core Time (ms) : 203.19 TIDL Subgraphs Processing Time (ms) : 203.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85818469 bytes MEM: Free's : 26 free's of 85818469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_603] | 1 | True | 0.31 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d75cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1198s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001539646122511257 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 210.62 Core Time (ms) : 209.29 TIDL Subgraphs Processing Time (ms) : 209.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42960629 bytes MEM: Free's : 26 free's of 42960629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1358] | 1 | True | 0.97 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686904000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015909125972881404 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 801.57 Core Time (ms) : 795.45 TIDL Subgraphs Processing Time (ms) : 795.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 161640025 bytes MEM: Free's : 26 free's of 161640025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_795] | 0 | - | 0.07 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d74ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.94 Core Time (ms) : 3.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1182] | 0 | - | 0.02 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c8fbc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1323] | 1 | True | 0.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d76db0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015617673525854787 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.29 Core Time (ms) : 13.72 TIDL Subgraphs Processing Time (ms) : 13.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27193957 bytes MEM: Free's : 26 free's of 27193957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_166] | 1 | True | 0.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237d7eca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013933476867388042 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.41 Core Time (ms) : 47.11 TIDL Subgraphs Processing Time (ms) : 47.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21523403 bytes MEM: Free's : 26 free's of 21523403 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_120] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b8e590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.457202305351972e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_832] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686cb4e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.200s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.030391761149872e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.16 Core Time (ms) : 5.75 TIDL Subgraphs Processing Time (ms) : 5.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16483493 bytes MEM: Free's : 26 free's of 16483493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_56] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b8d1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_719] | 1 | True | 1.62 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c77670 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.65s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017022096141174642 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1443.71 Core Time (ms) : 1436.51 TIDL Subgraphs Processing Time (ms) : 1436.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 182176769 bytes MEM: Free's : 26 free's of 182176769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_81] | 1 | True | 0.82 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c802f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2165s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017170423298476856 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 527.87 Core Time (ms) : 511.81 TIDL Subgraphs Processing Time (ms) : 511.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 372086069 bytes MEM: Free's : 26 free's of 372086069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1088] | 1 | True | 0.09 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b8c650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.66s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1185s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.463961115225985e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.91 Core Time (ms) : 0.86 TIDL Subgraphs Processing Time (ms) : 0.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13517717 bytes MEM: Free's : 26 free's of 13517717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1480] | 1 | True | 0.13 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b97730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013858173717742864 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.22 Core Time (ms) : 9.05 TIDL Subgraphs Processing Time (ms) : 9.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18132989 bytes MEM: Free's : 26 free's of 18132989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_948] | 0 | - | 0.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c85700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.71 Core Time (ms) : 1.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1181] | 1 | True | 0.11 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686bbfad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.319403442430999e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.04 Core Time (ms) : 15.96 TIDL Subgraphs Processing Time (ms) : 15.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20330709 bytes MEM: Free's : 26 free's of 20330709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_943] | 0 | - | 0.03 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686b99980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1025] | 1 | True | 0.16 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c88b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016239039426915378 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.09 Core Time (ms) : 35.50 TIDL Subgraphs Processing Time (ms) : 35.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72906685 bytes MEM: Free's : 26 free's of 72906685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_880] | 0 | - | 0.03 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f460abf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3903893275778317e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_520] | 1 | True | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0094b250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001757277067837513 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.88 Core Time (ms) : 7.61 TIDL Subgraphs Processing Time (ms) : 7.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26160992 bytes MEM: Free's : 26 free's of 26160992 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1442] | 0 | - | 0.05 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008638d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_805] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc008642b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00012662187436427008 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.04 Core Time (ms) : 2.95 TIDL Subgraphs Processing Time (ms) : 2.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17084829 bytes MEM: Free's : 26 free's of 17084829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1082] | 0 | - | 0.08 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009502a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.404403900692598e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.74 Core Time (ms) : 5.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1019] | 1 | True | 0.13 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00952e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000172343603637557 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.22 Core Time (ms) : 26.09 TIDL Subgraphs Processing Time (ms) : 26.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39623641 bytes MEM: Free's : 26 free's of 39623641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_48] | 0 | - | 0.05 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00955d20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 6.7723851954958484e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_236] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00955190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.5661664360720583e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.79 Core Time (ms) : 0.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_954] | 1 | True | 0.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0086e850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016951322697338674 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.30 Core Time (ms) : 44.06 TIDL Subgraphs Processing Time (ms) : 43.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103430157 bytes MEM: Free's : 26 free's of 103430157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_502] | 0 | - | 0.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00957ee0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_594] | 0 | - | 0.06 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009597b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 8.297701586913644e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.15 Core Time (ms) : 2.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_587] | 1 | True | 0.84 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009643f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016121335956537411 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 572.66 Core Time (ms) : 559.22 TIDL Subgraphs Processing Time (ms) : 558.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 315255949 bytes MEM: Free's : 26 free's of 315255949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_519] | 1 | True | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0095be60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015685323504906353 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.73 Core Time (ms) : 7.46 TIDL Subgraphs Processing Time (ms) : 7.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25728461 bytes MEM: Free's : 26 free's of 25728461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_771] | 1 | True | 0.41 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0086c780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001481968261115395 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 296.47 Core Time (ms) : 295.67 TIDL Subgraphs Processing Time (ms) : 295.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35835957 bytes MEM: Free's : 26 free's of 35835957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_856] | 1 | True | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0087abd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.509971277576335e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.03 Core Time (ms) : 17.15 TIDL Subgraphs Processing Time (ms) : 17.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28952053 bytes MEM: Free's : 26 free's of 28952053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1237] | 1 | True | 0.09 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009683b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011155328095958557 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.34 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12433125 bytes MEM: Free's : 26 free's of 12433125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1368] | 1 | True | 0.14 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00982150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015545377315306534 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.49 Core Time (ms) : 31.38 TIDL Subgraphs Processing Time (ms) : 31.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19731765 bytes MEM: Free's : 26 free's of 19731765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1101] | 1 | True | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc00967350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0020274558336683813 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.50 Core Time (ms) : 14.23 TIDL Subgraphs Processing Time (ms) : 14.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28625973 bytes MEM: Free's : 26 free's of 28625973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_428] | 0 | - | 0.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0087dc70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_760] | 0 | - | 0.05 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc009c5280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 5.92642717137541e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.50 Core Time (ms) : 2.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_766] | 0 | - | 0.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0087fc50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_309] | 1 | True | 1.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0096e810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1195s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1197s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0005298841479595577 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 656.88 Core Time (ms) : 620.70 TIDL Subgraphs Processing Time (ms) : 618.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 831955717 bytes MEM: Free's : 26 free's of 831955717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_270] | 0 | - | 0.06 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0096ba90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.2727493383100056e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.88 Core Time (ms) : 3.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1067] | 1 | True | 2.70 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0096caf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0009508132172044736 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2117.37 Core Time (ms) : 2081.87 TIDL Subgraphs Processing Time (ms) : 2079.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 841841633 bytes MEM: Free's : 26 free's of 841841633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1456] | 1 | True | 0.26 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6eed3f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017055122330831342 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 130.65 Core Time (ms) : 127.33 TIDL Subgraphs Processing Time (ms) : 127.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88115697 bytes MEM: Free's : 26 free's of 88115697 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1245] | 1 | True | 0.12 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c7038730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001511473613658551 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.59 Core Time (ms) : 29.43 TIDL Subgraphs Processing Time (ms) : 29.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18203259 bytes MEM: Free's : 26 free's of 18203259 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1125] | 1 | True | 0.13 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6ee8980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013851572600834453 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.51 Core Time (ms) : 21.36 TIDL Subgraphs Processing Time (ms) : 21.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22277937 bytes MEM: Free's : 26 free's of 22277937 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_172] | 0 | - | 0.06 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6eedc90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4383530422462186e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.98 Core Time (ms) : 0.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_331] | 0 | - | 0.05 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fdf360 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.37 Core Time (ms) : 2.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_475] | 1 | True | 0.13 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fd68c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015059487830908092 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.89 Core Time (ms) : 26.64 TIDL Subgraphs Processing Time (ms) : 26.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24754197 bytes MEM: Free's : 26 free's of 24754197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_539] | 1 | True | 0.13 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6eeef90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011379107408058524 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.36 Core Time (ms) : 16.14 TIDL Subgraphs Processing Time (ms) : 16.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38566129 bytes MEM: Free's : 26 free's of 38566129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1205] | 1 | True | 0.13 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fdfa30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001511379695384772 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.19 Core Time (ms) : 44.95 TIDL Subgraphs Processing Time (ms) : 44.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28430485 bytes MEM: Free's : 26 free's of 28430485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_146] | 1 | True | 0.12 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae800898ed0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.214s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001476671948678811 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.55 Core Time (ms) : 15.40 TIDL Subgraphs Processing Time (ms) : 15.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15356997 bytes MEM: Free's : 26 free's of 15356997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_216] | 0 | - | 0.08 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6c77be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.673547116396422e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.87 Core Time (ms) : 5.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_277] | 1 | True | 0.46 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fddaf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.149s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013769864220552425 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 363.03 Core Time (ms) : 361.84 TIDL Subgraphs Processing Time (ms) : 361.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39641405 bytes MEM: Free's : 26 free's of 39641405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1433] | 0 | - | 0.03 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008e5ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_255] | 1 | True | 0.12 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6ef5c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001456761604962654 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.59 Core Time (ms) : 17.48 TIDL Subgraphs Processing Time (ms) : 17.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17910113 bytes MEM: Free's : 26 free's of 17910113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_274] | 0 | - | 0.08 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fe2270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3017050515452138e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.87 Core Time (ms) : 4.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_234] | 1 | True | 4.80 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6c088b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015667250390585227 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4556.93 Core Time (ms) : 4545.11 TIDL Subgraphs Processing Time (ms) : 4544.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 282748937 bytes MEM: Free's : 26 free's of 282748937 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1383] | 0 | - | 0.02 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6ad670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.0642904764533377e-16 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.24 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1147] | 1 | True | 7.41 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e3cfdb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1214s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016140436091921075 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6868.89 Core Time (ms) : 6833.89 TIDL Subgraphs Processing Time (ms) : 6833.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 782241853 bytes MEM: Free's : 26 free's of 782241853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1283] | 1 | True | 4.90 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6c07c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001598464266676966 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4593.97 Core Time (ms) : 4577.45 TIDL Subgraphs Processing Time (ms) : 4576.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 314583037 bytes MEM: Free's : 26 free's of 314583037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1364] | 0 | - | 0.05 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d1af510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.03 Core Time (ms) : 3.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1352] | 1 | True | 0.17 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77767f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1201s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001613037864534725 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 88.85 Core Time (ms) : 87.90 TIDL Subgraphs Processing Time (ms) : 87.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36931125 bytes MEM: Free's : 26 free's of 36931125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1221] | 1 | True | 0.29 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77768f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1254s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014984232797610498 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 196.53 Core Time (ms) : 195.36 TIDL Subgraphs Processing Time (ms) : 195.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52289617 bytes MEM: Free's : 26 free's of 52289617 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_919] | 1 | True | 0.52 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da71a8e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017663212431873396 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 328.76 Core Time (ms) : 319.87 TIDL Subgraphs Processing Time (ms) : 319.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 197969493 bytes MEM: Free's : 26 free's of 197969493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1131] | 1 | True | 0.33 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7776c300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0016771711097367799 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 222.33 Core Time (ms) : 220.05 TIDL Subgraphs Processing Time (ms) : 219.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64701125 bytes MEM: Free's : 26 free's of 64701125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1060] | 1 | True | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7979b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001482204059799389 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 104.75 Core Time (ms) : 102.50 TIDL Subgraphs Processing Time (ms) : 102.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63950430 bytes MEM: Free's : 26 free's of 63950430 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1301] | 0 | - | 0.03 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda77683320 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_445] | 1 | True | 0.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda776cfb80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017863507684777853 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.93 Core Time (ms) : 1.86 TIDL Subgraphs Processing Time (ms) : 1.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14482669 bytes MEM: Free's : 26 free's of 14482669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_218] | 1 | True | 0.13 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da73c730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1496s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014843947158835855 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.23 Core Time (ms) : 53.05 TIDL Subgraphs Processing Time (ms) : 53.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19202925 bytes MEM: Free's : 26 free's of 19202925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_956] | 1 | True | 0.22 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda776886d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018513211692077074 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.62 Core Time (ms) : 59.87 TIDL Subgraphs Processing Time (ms) : 59.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 117983053 bytes MEM: Free's : 26 free's of 117983053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_638] | 0 | - | 0.04 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da9d2160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_492] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6b0740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012223752042047995 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.59 Core Time (ms) : 7.36 TIDL Subgraphs Processing Time (ms) : 7.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17553125 bytes MEM: Free's : 26 free's of 17553125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1041] | 1 | True | 0.11 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6358d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016611957957537218 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.72 Core Time (ms) : 17.05 TIDL Subgraphs Processing Time (ms) : 17.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29091065 bytes MEM: Free's : 26 free's of 29091065 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1192] | 1 | True | 0.13 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6b0940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01838956468346714 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.64 Core Time (ms) : 41.85 TIDL Subgraphs Processing Time (ms) : 41.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29349653 bytes MEM: Free's : 26 free's of 29349653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_494] | 0 | - | 0.04 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da639de0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_583] | 1 | True | 0.85 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da72bc20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017352955279525685 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 586.84 Core Time (ms) : 574.36 TIDL Subgraphs Processing Time (ms) : 573.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 311578765 bytes MEM: Free's : 26 free's of 311578765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1351] | 0 | - | 0.02 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7d0a80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_204] | 0 | - | 0.03 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6d54d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.62 Core Time (ms) : 3.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_755] | 1 | True | 2.66 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e43fd20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001647794497766644 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2526.33 Core Time (ms) : 2522.16 TIDL Subgraphs Processing Time (ms) : 2522.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 120488536 bytes MEM: Free's : 26 free's of 120488536 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_905] | 1 | True | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc39a280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016851654705925742 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 161.49 Core Time (ms) : 159.61 TIDL Subgraphs Processing Time (ms) : 159.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52221781 bytes MEM: Free's : 26 free's of 52221781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_662] | 0 | - | 0.02 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da644210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.9935356539786204e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.09 Core Time (ms) : 2.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_590] | 0 | - | 0.03 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6dd190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_319] | 1 | True | 0.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afabb40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1686s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00048056225385371444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 187.15 Core Time (ms) : 180.45 TIDL Subgraphs Processing Time (ms) : 180.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 158001245 bytes MEM: Free's : 26 free's of 158001245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1354] | 1 | True | 0.11 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da640e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.020384879505977782 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.91 Core Time (ms) : 17.75 TIDL Subgraphs Processing Time (ms) : 17.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21343541 bytes MEM: Free's : 26 free's of 21343541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_652] | 1 | True | 1.42 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbfb15c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015948877223798512 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1272.71 Core Time (ms) : 1266.84 TIDL Subgraphs Processing Time (ms) : 1266.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 129177113 bytes MEM: Free's : 26 free's of 129177113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_365] | 1 | True | 0.42 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da3c0400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005494390381874478 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 308.19 Core Time (ms) : 306.32 TIDL Subgraphs Processing Time (ms) : 306.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55728845 bytes MEM: Free's : 26 free's of 55728845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_987] | 1 | True | 0.11 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afc4360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001463190499676981 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.49 Core Time (ms) : 21.32 TIDL Subgraphs Processing Time (ms) : 21.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20119445 bytes MEM: Free's : 26 free's of 20119445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_108] | 0 | - | 0.03 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aebd6a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1196] | 1 | True | 0.15 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aec48a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011324912558081419 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.79 Core Time (ms) : 65.11 TIDL Subgraphs Processing Time (ms) : 65.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24915705 bytes MEM: Free's : 26 free's of 24915705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_753] | 1 | True | 0.09 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6f03070 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.59s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001390205281449286 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.87 Core Time (ms) : 14.73 TIDL Subgraphs Processing Time (ms) : 14.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17592325 bytes MEM: Free's : 26 free's of 17592325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_881] | 1 | True | 0.12 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da640550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014939329212472962 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.96 Core Time (ms) : 36.66 TIDL Subgraphs Processing Time (ms) : 36.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24206301 bytes MEM: Free's : 26 free's of 24206301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_138] | 1 | True | 1.84 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6c07c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1380s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016447450389477225 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1627.52 Core Time (ms) : 1617.68 TIDL Subgraphs Processing Time (ms) : 1617.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 228055353 bytes MEM: Free's : 26 free's of 228055353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_691] | 1 | True | 6.61 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529abce660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016953719420191476 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6154.46 Core Time (ms) : 6126.79 TIDL Subgraphs Processing Time (ms) : 6125.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 647133005 bytes MEM: Free's : 26 free's of 647133005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_378] | 1 | True | 0.08 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da6473b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014750721026853168 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.27 Core Time (ms) : 11.04 TIDL Subgraphs Processing Time (ms) : 11.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17895797 bytes MEM: Free's : 26 free's of 17895797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_206] | 1 | True | 0.33 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da72df20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015434645020173413 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 231.04 Core Time (ms) : 230.18 TIDL Subgraphs Processing Time (ms) : 230.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36190077 bytes MEM: Free's : 26 free's of 36190077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1240] | 1 | True | 0.07 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e87aac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000105893092509931 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.29 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12390421 bytes MEM: Free's : 26 free's of 12390421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_986] | 1 | True | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e78f020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1291s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016209814206375 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 157.93 Core Time (ms) : 153.69 TIDL Subgraphs Processing Time (ms) : 153.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 104402765 bytes MEM: Free's : 26 free's of 104402765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1476] | 1 | True | 0.08 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6011da63af80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014905311220796355 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.82 Core Time (ms) : 4.72 TIDL Subgraphs Processing Time (ms) : 4.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15050529 bytes MEM: Free's : 26 free's of 15050529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_491] | 1 | True | 0.13 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e87caa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003330577246509247 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.34 Core Time (ms) : 44.78 TIDL Subgraphs Processing Time (ms) : 44.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26176061 bytes MEM: Free's : 26 free's of 26176061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_806] | 0 | - | 0.04 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e87e800 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.91 Core Time (ms) : 1.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1322] | 1 | True | 0.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc39ddb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001563008860944449 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.35 Core Time (ms) : 29.23 TIDL Subgraphs Processing Time (ms) : 29.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39546693 bytes MEM: Free's : 26 free's of 39546693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1344] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc599510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015406640550313607 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.84 Core Time (ms) : 20.73 TIDL Subgraphs Processing Time (ms) : 20.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20282909 bytes MEM: Free's : 26 free's of 20282909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_421] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc39e560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_879] | 1 | True | 0.98 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbfb99e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015919613876446288 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 833.57 Core Time (ms) : 828.40 TIDL Subgraphs Processing Time (ms) : 828.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 130366853 bytes MEM: Free's : 26 free's of 130366853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_980] | 0 | - | 0.03 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6ba9a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_121] | 1 | True | 8.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e43f6d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0009685384353188433 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7299.80 Core Time (ms) : 7240.48 TIDL Subgraphs Processing Time (ms) : 7238.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1193230325 bytes MEM: Free's : 26 free's of 1193230325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1302] | 1 | True | 0.11 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164f02720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016577035788026915 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.77 Core Time (ms) : 25.63 TIDL Subgraphs Processing Time (ms) : 25.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40002597 bytes MEM: Free's : 26 free's of 40002597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_420] | 0 | - | 0.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090c9afa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1113] | 1 | True | 0.12 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3a3e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1223s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1225s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001557964994533766 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.02 Core Time (ms) : 42.80 TIDL Subgraphs Processing Time (ms) : 42.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24133821 bytes MEM: Free's : 26 free's of 24133821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1345] | 0 | - | 0.02 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2c2770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1250] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbfbe730 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1448] | 1 | True | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2c2f60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001531297846331523 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.05 Core Time (ms) : 12.50 TIDL Subgraphs Processing Time (ms) : 12.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26206401 bytes MEM: Free's : 26 free's of 26206401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_80] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc65a7a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_729] | 1 | True | 0.31 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bbfc1b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014684023760179774 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 226.40 Core Time (ms) : 225.38 TIDL Subgraphs Processing Time (ms) : 225.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37565461 bytes MEM: Free's : 26 free's of 37565461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_354] | 1 | True | 0.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc2c7770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.930367681845565e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.45 Core Time (ms) : 24.59 TIDL Subgraphs Processing Time (ms) : 24.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33195637 bytes MEM: Free's : 26 free's of 33195637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1377] | 0 | - | 0.03 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a97c690 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_750] | 0 | - | 0.04 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529abcdfd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.410948899937222e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.67 Core Time (ms) : 2.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_289] | 1 | True | 0.12 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aecad80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04083974581248709 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.53 Core Time (ms) : 16.29 TIDL Subgraphs Processing Time (ms) : 16.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59190053 bytes MEM: Free's : 26 free's of 59190053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1194] | 0 | - | 0.04 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ac0ac60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.687742309509814e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.72 Core Time (ms) : 1.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_322] | 1 | True | 0.07 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aecc9f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.962872661580113e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.20 Core Time (ms) : 1.12 TIDL Subgraphs Processing Time (ms) : 1.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14207365 bytes MEM: Free's : 26 free's of 14207365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_745] | 1 | True | 0.08 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529af20470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1217s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001562165000840261 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.82 Core Time (ms) : 7.72 TIDL Subgraphs Processing Time (ms) : 7.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14556829 bytes MEM: Free's : 26 free's of 14556829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_162] | 1 | True | 2.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529ac4e7b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015926026594509642 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2007.13 Core Time (ms) : 1991.96 TIDL Subgraphs Processing Time (ms) : 1991.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 266669733 bytes MEM: Free's : 26 free's of 266669733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_711] | 1 | True | 0.43 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bae930c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.463782758562593e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 318.18 Core Time (ms) : 315.16 TIDL Subgraphs Processing Time (ms) : 315.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 91509285 bytes MEM: Free's : 26 free's of 91509285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1458] | 1 | True | 0.58 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bae93030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.003713544040306702 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 422.19 Core Time (ms) : 416.81 TIDL Subgraphs Processing Time (ms) : 416.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 146408405 bytes MEM: Free's : 26 free's of 146408405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_372] | 1 | True | 0.07 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8105ce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.029012349925644318 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.79 Core Time (ms) : 1.74 TIDL Subgraphs Processing Time (ms) : 1.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14000729 bytes MEM: Free's : 26 free's of 14000729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_380] | 1 | True | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece810ff00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.381467397926778e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 136.55 Core Time (ms) : 132.93 TIDL Subgraphs Processing Time (ms) : 132.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83695653 bytes MEM: Free's : 26 free's of 83695653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_473] | 1 | True | 0.10 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb153e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1452s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015243204041199505 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.71 Core Time (ms) : 8.55 TIDL Subgraphs Processing Time (ms) : 8.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17494141 bytes MEM: Free's : 26 free's of 17494141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_610] | 0 | - | 0.04 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb23dd80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_272] | 0 | - | 0.03 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece834e040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.91449483617507e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.24 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1362] | 1 | True | 0.16 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece81f5780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0034308404520726875 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.81 Core Time (ms) : 69.66 TIDL Subgraphs Processing Time (ms) : 69.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38304885 bytes MEM: Free's : 26 free's of 38304885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_644] | 1 | True | 0.75 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a24c620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016340327737199224 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 618.58 Core Time (ms) : 614.70 TIDL Subgraphs Processing Time (ms) : 614.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81309174 bytes MEM: Free's : 26 free's of 81309174 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_173] | 1 | True | 0.48 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece810e610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016162361912292684 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 333.36 Core Time (ms) : 319.68 TIDL Subgraphs Processing Time (ms) : 319.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 94790901 bytes MEM: Free's : 26 free's of 94790901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1014] | 0 | - | 0.02 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6c4b80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.25 Core Time (ms) : 3.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_180] | 0 | - | 0.03 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7ab080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4429670498339682e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_810] | 1 | True | 0.09 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aed6290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1603s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013519787345533092 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.54 Core Time (ms) : 4.38 TIDL Subgraphs Processing Time (ms) : 4.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17706173 bytes MEM: Free's : 26 free's of 17706173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_13] | 1 | True | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6bc7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011706259668020523 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.03 Core Time (ms) : 60.42 TIDL Subgraphs Processing Time (ms) : 60.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 126215533 bytes MEM: Free's : 26 free's of 126215533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_624] | 1 | True | 0.07 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aedb730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00011285906324967069 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.07 Core Time (ms) : 1.02 TIDL Subgraphs Processing Time (ms) : 0.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13389947 bytes MEM: Free's : 26 free's of 13389947 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_418] | 1 | True | 0.13 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afcb8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015357962168669457 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.75 Core Time (ms) : 40.24 TIDL Subgraphs Processing Time (ms) : 40.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30659321 bytes MEM: Free's : 26 free's of 30659321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1431] | 1 | True | 0.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece810e7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1472s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008248422370669143 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.06 Core Time (ms) : 2.87 TIDL Subgraphs Processing Time (ms) : 2.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16977377 bytes MEM: Free's : 26 free's of 16977377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_527] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6bda40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001675393048097 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.95 Core Time (ms) : 10.34 TIDL Subgraphs Processing Time (ms) : 10.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29344837 bytes MEM: Free's : 26 free's of 29344837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_655] | 1 | True | 0.46 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afc60c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015734008166498148 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 360.21 Core Time (ms) : 357.57 TIDL Subgraphs Processing Time (ms) : 357.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63055675 bytes MEM: Free's : 26 free's of 63055675 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_294] | 1 | True | 0.08 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e92db60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014481416180167476 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.03 Core Time (ms) : 3.84 TIDL Subgraphs Processing Time (ms) : 3.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23872205 bytes MEM: Free's : 26 free's of 23872205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1171] | 1 | True | 3.94 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e763c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1603s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001663753546303543 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3564.64 Core Time (ms) : 3546.78 TIDL Subgraphs Processing Time (ms) : 3545.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 456558309 bytes MEM: Free's : 26 free's of 456558309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_735] | 1 | True | 2.45 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e3cf160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017347168433130524 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2285.80 Core Time (ms) : 2279.82 TIDL Subgraphs Processing Time (ms) : 2279.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 156953057 bytes MEM: Free's : 26 free's of 156953057 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_2] | 1 | True | 0.08 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529b038c90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014010494593479032 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.13 Core Time (ms) : 1.06 TIDL Subgraphs Processing Time (ms) : 1.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14205157 bytes MEM: Free's : 26 free's of 14205157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_275] | 1 | True | 0.13 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529abea100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004514585650645262 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.80 Core Time (ms) : 59.61 TIDL Subgraphs Processing Time (ms) : 59.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22870245 bytes MEM: Free's : 26 free's of 22870245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1017] | 1 | True | 0.08 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529afd73c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02091742892385916 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.26 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18883333 bytes MEM: Free's : 26 free's of 18883333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_110] | 1 | True | 0.14 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7ade60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008305576174623984 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.55 Core Time (ms) : 66.34 TIDL Subgraphs Processing Time (ms) : 66.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24124296 bytes MEM: Free's : 26 free's of 24124296 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_872] | 1 | True | 0.17 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7b02b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014255189190191496 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 82.56 Core Time (ms) : 81.37 TIDL Subgraphs Processing Time (ms) : 81.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39520773 bytes MEM: Free's : 26 free's of 39520773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_470] | 1 | True | 0.11 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6ccb70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0005449449318873776 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.24 Core Time (ms) : 22.47 TIDL Subgraphs Processing Time (ms) : 22.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29702013 bytes MEM: Free's : 26 free's of 29702013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_126] | 1 | True | 0.07 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6cc510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0025047099965447156 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.46 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12736109 bytes MEM: Free's : 26 free's of 12736109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_268] | 0 | - | 0.02 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7b5980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1341] | 1 | True | 0.14 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6cfa00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.052754682684196e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.01 Core Time (ms) : 38.47 TIDL Subgraphs Processing Time (ms) : 38.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52892453 bytes MEM: Free's : 26 free's of 52892453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_396] | 0 | - | 0.03 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6cf210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_931] | 1 | True | 0.11 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7b9860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00018341859995132435 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.61 Core Time (ms) : 13.60 TIDL Subgraphs Processing Time (ms) : 13.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57408693 bytes MEM: Free's : 26 free's of 57408693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_714] | 0 | - | 0.03 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6d9c30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.75 Core Time (ms) : 7.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_692] | 1 | True | 0.07 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6d3c70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 6.565642695229646e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.09 Core Time (ms) : 5.80 TIDL Subgraphs Processing Time (ms) : 5.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14833621 bytes MEM: Free's : 26 free's of 14833621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_925] | 0 | - | 0.07 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7beba0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.93 Core Time (ms) : 3.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_408] | 1 | True | 0.16 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7bf210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016459488020838248 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.60 Core Time (ms) : 49.03 TIDL Subgraphs Processing Time (ms) : 48.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72501725 bytes MEM: Free's : 26 free's of 72501725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_802] | 1 | True | 0.09 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6d7620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4806265167153676 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.49 Core Time (ms) : 4.14 TIDL Subgraphs Processing Time (ms) : 4.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25363437 bytes MEM: Free's : 26 free's of 25363437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1464] | 1 | True | 0.09 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7244f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011078612535992322 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.86 Core Time (ms) : 2.76 TIDL Subgraphs Processing Time (ms) : 2.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14789037 bytes MEM: Free's : 26 free's of 14789037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_531] | 1 | True | 0.88 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a254130 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016715543936923023 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 621.04 Core Time (ms) : 609.32 TIDL Subgraphs Processing Time (ms) : 608.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 283231633 bytes MEM: Free's : 26 free's of 283231633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1444] | 1 | True | 0.12 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7d2d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001489566773655453 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.84 Core Time (ms) : 32.95 TIDL Subgraphs Processing Time (ms) : 32.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29609329 bytes MEM: Free's : 26 free's of 29609329 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_186] | 1 | True | 0.56 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7c9eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5927s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015746894805299306 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 445.29 Core Time (ms) : 442.29 TIDL Subgraphs Processing Time (ms) : 442.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64907761 bytes MEM: Free's : 26 free's of 64907761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1124] | 1 | True | 0.12 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6e6880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6040s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00999093463675503 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.38 Core Time (ms) : 23.87 TIDL Subgraphs Processing Time (ms) : 23.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24479717 bytes MEM: Free's : 26 free's of 24479717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_824] | 1 | True | 0.10 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb4190b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017136594093393419 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.25 Core Time (ms) : 10.99 TIDL Subgraphs Processing Time (ms) : 10.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28565253 bytes MEM: Free's : 26 free's of 28565253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_888] | 1 | True | 0.08 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e731d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013325048096132652 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.58 Core Time (ms) : 4.49 TIDL Subgraphs Processing Time (ms) : 4.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14399133 bytes MEM: Free's : 26 free's of 14399133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1115] | 1 | True | 0.24 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a170fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006774140654593344 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 133.79 Core Time (ms) : 131.13 TIDL Subgraphs Processing Time (ms) : 131.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63471225 bytes MEM: Free's : 26 free's of 63471225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_721] | 1 | True | 0.20 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7d02d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014442420339785432 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 97.16 Core Time (ms) : 96.40 TIDL Subgraphs Processing Time (ms) : 96.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31531371 bytes MEM: Free's : 26 free's of 31531371 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_778] | 0 | - | 0.05 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e3e9920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.76 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1346] | 1 | True | 0.14 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6f0e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 9.456961645057573e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.78 Core Time (ms) : 43.48 TIDL Subgraphs Processing Time (ms) : 43.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39251621 bytes MEM: Free's : 26 free's of 39251621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_820] | 0 | - | 0.03 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a16f970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_751] | 1 | True | 0.34 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7d67c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015108948413812263 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 257.78 Core Time (ms) : 257.20 TIDL Subgraphs Processing Time (ms) : 257.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27346549 bytes MEM: Free's : 26 free's of 27346549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_71] | 1 | True | 0.08 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1641e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06448632492663496 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.16 Core Time (ms) : 3.05 TIDL Subgraphs Processing Time (ms) : 3.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14930054 bytes MEM: Free's : 26 free's of 14930054 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1026] | 0 | - | 0.02 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a178720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 2.2574051641827226e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_25] | 1 | True | 0.13 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a2619c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001660896551908428 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.17 Core Time (ms) : 31.82 TIDL Subgraphs Processing Time (ms) : 31.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43824309 bytes MEM: Free's : 26 free's of 43824309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1030] | 0 | - | 0.04 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6ef5b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.6377623543121322e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.24 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_189] | 1 | True | 0.08 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7e0590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1198s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.014518445773470372 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.88 Core Time (ms) : 7.63 TIDL Subgraphs Processing Time (ms) : 7.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17961405 bytes MEM: Free's : 26 free's of 17961405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_551] | 1 | True | 0.53 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a266100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001599989825979314 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 351.16 Core Time (ms) : 343.68 TIDL Subgraphs Processing Time (ms) : 343.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 172017499 bytes MEM: Free's : 26 free's of 172017499 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_672] | 1 | True | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6f6710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015594624546350183 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.38 Core Time (ms) : 27.25 TIDL Subgraphs Processing Time (ms) : 27.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18725805 bytes MEM: Free's : 26 free's of 18725805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1316] | 1 | True | 0.12 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7e46f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016076096474360824 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.34 Core Time (ms) : 34.73 TIDL Subgraphs Processing Time (ms) : 34.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 45882389 bytes MEM: Free's : 26 free's of 45882389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_792] | 0 | - | 0.04 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e8201d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1068] | 1 | True | 0.09 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6f8af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006684410299048551 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.81 Core Time (ms) : 11.92 TIDL Subgraphs Processing Time (ms) : 11.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31721205 bytes MEM: Free's : 26 free's of 31721205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1111] | 1 | True | 0.15 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7e44b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004140945784402334 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 57.99 Core Time (ms) : 57.68 TIDL Subgraphs Processing Time (ms) : 57.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25478109 bytes MEM: Free's : 26 free's of 25478109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_184] | 0 | - | 0.02 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48edaed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_576] | 1 | True | 0.37 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fc8f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001600618640322007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 211.30 Core Time (ms) : 205.56 TIDL Subgraphs Processing Time (ms) : 205.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 138792181 bytes MEM: Free's : 26 free's of 138792181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1387] | 0 | - | 0.07 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e7af20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.30 Core Time (ms) : 3.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_628] | 1 | True | 0.12 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e6fde40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013709487154885952 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.35 Core Time (ms) : 23.21 TIDL Subgraphs Processing Time (ms) : 23.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18867729 bytes MEM: Free's : 26 free's of 18867729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1356] | 1 | True | 0.16 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a17ceb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011406740765699213 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.66 Core Time (ms) : 66.40 TIDL Subgraphs Processing Time (ms) : 66.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39751817 bytes MEM: Free's : 26 free's of 39751817 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_229] | 1 | True | 4.67 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e3fd300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016360754870438116 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4294.85 Core Time (ms) : 4269.50 TIDL Subgraphs Processing Time (ms) : 4268.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 504769813 bytes MEM: Free's : 26 free's of 504769813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_814] | 0 | - | 0.03 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a17f220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_89] | 1 | True | 0.10 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a266f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014649218377570707 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.80 Core Time (ms) : 13.35 TIDL Subgraphs Processing Time (ms) : 13.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20996837 bytes MEM: Free's : 26 free's of 20996837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_734] | 0 | - | 0.02 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48edd9f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 4.26398961323048e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_730] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ed89b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7842901431887718e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_971] | 1 | True | 0.08 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a2824d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001588408716760013 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.76 Core Time (ms) : 10.61 TIDL Subgraphs Processing Time (ms) : 10.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19190037 bytes MEM: Free's : 26 free's of 19190037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_21] | 1 | True | 0.08 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48edb920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.029791670220959084 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.93 Core Time (ms) : 1.79 TIDL Subgraphs Processing Time (ms) : 1.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20849941 bytes MEM: Free's : 26 free's of 20849941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1081] | 1 | True | 0.09 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a188d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 9.001412265913501e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.94 Core Time (ms) : 9.68 TIDL Subgraphs Processing Time (ms) : 9.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23972821 bytes MEM: Free's : 26 free's of 23972821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_758] | 0 | - | 0.02 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ee17d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1211] | 1 | True | 1.56 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48bdd970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004250637559677457 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1394.44 Core Time (ms) : 1387.87 TIDL Subgraphs Processing Time (ms) : 1387.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 180683797 bytes MEM: Free's : 26 free's of 180683797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_717] | 1 | True | 0.91 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f7689e84e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001578539295911307 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 788.91 Core Time (ms) : 785.66 TIDL Subgraphs Processing Time (ms) : 785.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63876765 bytes MEM: Free's : 26 free's of 63876765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_894] | 0 | - | 0.02 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a1803f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1435] | 1 | True | 0.13 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a18a790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017565178018752957 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.24 Core Time (ms) : 26.56 TIDL Subgraphs Processing Time (ms) : 26.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67493949 bytes MEM: Free's : 26 free's of 67493949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_807] | 1 | True | 0.37 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fca930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1328s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017060135151249415 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 188.09 Core Time (ms) : 180.04 TIDL Subgraphs Processing Time (ms) : 179.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 203231541 bytes MEM: Free's : 26 free's of 203231541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1074] | 0 | - | 0.03 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fceaf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.4708506525790203e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_100] | 0 | - | 0.04 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48fcab10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 9.135735103686845e-15 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.67 Core Time (ms) : 1.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1075] | 1 | True | 3.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b97d8230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017017996791345087 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2501.86 Core Time (ms) : 2457.11 TIDL Subgraphs Processing Time (ms) : 2454.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 972687017 bytes MEM: Free's : 26 free's of 972687017 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_643] | 1 | True | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e702630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015802927133573615 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 163.19 Core Time (ms) : 160.72 TIDL Subgraphs Processing Time (ms) : 160.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62862717 bytes MEM: Free's : 26 free's of 62862717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_412] | 1 | True | 1.72 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7f5880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00028710284773305386 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1066.65 Core Time (ms) : 1024.28 TIDL Subgraphs Processing Time (ms) : 1021.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 874915429 bytes MEM: Free's : 26 free's of 874915429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_14] | 1 | True | 0.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9baea70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016235185799597522 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.99 Core Time (ms) : 65.96 TIDL Subgraphs Processing Time (ms) : 65.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60425322 bytes MEM: Free's : 26 free's of 60425322 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_181] | 1 | True | 3.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ee9b9807520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015693638984596724 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3066.31 Core Time (ms) : 3055.73 TIDL Subgraphs Processing Time (ms) : 3055.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 254104110 bytes MEM: Free's : 26 free's of 254104110 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1148] | 1 | True | 0.64 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e7eee50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001727617401523693 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 517.02 Core Time (ms) : 514.23 TIDL Subgraphs Processing Time (ms) : 514.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 79297270 bytes MEM: Free's : 26 free's of 79297270 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_444] | 1 | True | 0.15 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e709000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017243309732910915 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.46 Core Time (ms) : 39.17 TIDL Subgraphs Processing Time (ms) : 39.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64340241 bytes MEM: Free's : 26 free's of 64340241 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_757] | 1 | True | 0.07 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x62b80e713400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014135684971152456 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.85 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12911669 bytes MEM: Free's : 26 free's of 12911669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_570] | 0 | - | 0.02 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c92cf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_474] | 1 | True | 0.33 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c3237c92480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00016545939515704794 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 197.31 Core Time (ms) : 192.33 TIDL Subgraphs Processing Time (ms) : 192.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 128697853 bytes MEM: Free's : 26 free's of 128697853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_626] | 0 | - | 0.04 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f46f3e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3229567941915146e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.17 Core Time (ms) : 1.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_248] | 0 | - | 0.02 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f460fe40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 3.861682223085153e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.82 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1391] | 0 | - | 0.03 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6521f460e580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.91 Core Time (ms) : 0.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_194] | 1 | True | 0.08 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c893b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01889082575581079 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.93 Core Time (ms) : 7.76 TIDL Subgraphs Processing Time (ms) : 7.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 16147709 bytes MEM: Free's : 26 free's of 16147709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1223] | 1 | True | 0.99 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63f686c91650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015272115365474743 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 864.99 Core Time (ms) : 861.97 TIDL Subgraphs Processing Time (ms) : 861.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 85944181 bytes MEM: Free's : 26 free's of 85944181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_227] | 1 | True | 0.29 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60fc0059ae40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015847776156369418 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 191.76 Core Time (ms) : 190.48 TIDL Subgraphs Processing Time (ms) : 190.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37565461 bytes MEM: Free's : 26 free's of 37565461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1304] | 0 | - | 0.02 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae80095d5e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1231] | 1 | True | 0.10 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae800801950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3594s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 8.565640052555931e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.54 Core Time (ms) : 19.35 TIDL Subgraphs Processing Time (ms) : 19.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15172421 bytes MEM: Free's : 26 free's of 15172421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_617] | 1 | True | 0.32 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ae8008ecb20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014934483563918845 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 188.20 Core Time (ms) : 186.41 TIDL Subgraphs Processing Time (ms) : 186.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 62377745 bytes MEM: Free's : 26 free's of 62377745 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_233] | 1 | True | 0.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d5916d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013196427519103965 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.32 Core Time (ms) : 6.96 TIDL Subgraphs Processing Time (ms) : 6.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15804539 bytes MEM: Free's : 26 free's of 15804539 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1136] | 1 | True | 0.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d6baaa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006605273897460752 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.10 Core Time (ms) : 31.78 TIDL Subgraphs Processing Time (ms) : 31.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20712955 bytes MEM: Free's : 26 free's of 20712955 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_906] | 1 | True | 0.35 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d593e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1892s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1894s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000161625538700203 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 215.97 Core Time (ms) : 214.18 TIDL Subgraphs Processing Time (ms) : 214.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57774181 bytes MEM: Free's : 26 free's of 57774181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_708] | 1 | True | 0.22 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d592cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.64s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001453595715577346 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 117.51 Core Time (ms) : 116.90 TIDL Subgraphs Processing Time (ms) : 116.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25999787 bytes MEM: Free's : 26 free's of 25999787 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_178] | 1 | True | 0.10 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d3884098f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001362793527314704 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.38 Core Time (ms) : 22.22 TIDL Subgraphs Processing Time (ms) : 22.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18049061 bytes MEM: Free's : 26 free's of 18049061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1072] | 1 | True | 0.11 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d5ad470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015477484260422824 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.60 Core Time (ms) : 11.48 TIDL Subgraphs Processing Time (ms) : 11.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19179885 bytes MEM: Free's : 26 free's of 19179885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_763] | 1 | True | 0.11 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d4b2510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1175s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001377412265208625 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.49 Core Time (ms) : 2.44 TIDL Subgraphs Processing Time (ms) : 2.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13545877 bytes MEM: Free's : 26 free's of 13545877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_506] | 0 | - | 0.05 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58466d4b0eb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1450] | 1 | True | 0.13 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5eda7777df70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015079007154678896 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.39 Core Time (ms) : 37.37 TIDL Subgraphs Processing Time (ms) : 37.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35038165 bytes MEM: Free's : 26 free's of 35038165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_803] | 1 | True | 0.13 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63db1e79b270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5823s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017578887133316794 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.05 Core Time (ms) : 17.45 TIDL Subgraphs Processing Time (ms) : 17.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42463145 bytes MEM: Free's : 26 free's of 42463145 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_57] | 1 | True | 0.56 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143631dd650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031950721161184953 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 325.44 Core Time (ms) : 315.83 TIDL Subgraphs Processing Time (ms) : 315.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 210100577 bytes MEM: Free's : 26 free's of 210100577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_908] | 1 | True | 0.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e1164f0ab30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00020537826330138006 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.72 Core Time (ms) : 53.31 TIDL Subgraphs Processing Time (ms) : 53.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 191139589 bytes MEM: Free's : 26 free's of 191139589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_30] | 1 | True | 0.17 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5870c6fef240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001685386617691044 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.37 Core Time (ms) : 50.95 TIDL Subgraphs Processing Time (ms) : 50.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 63743280 bytes MEM: Free's : 26 free's of 63743280 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_249] | 1 | True | 0.60 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614362df3a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2104s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015367076092152383 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 464.42 Core Time (ms) : 461.01 TIDL Subgraphs Processing Time (ms) : 460.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 91554501 bytes MEM: Free's : 26 free's of 91554501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1279] | 1 | True | 0.15 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f5090ca8510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007992717899014828 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 69.92 Core Time (ms) : 69.52 TIDL Subgraphs Processing Time (ms) : 69.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25162318 bytes MEM: Free's : 26 free's of 25162318 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_616] | 1 | True | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6143630f7c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015183997511036766 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 79.52 Core Time (ms) : 78.26 TIDL Subgraphs Processing Time (ms) : 78.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44207405 bytes MEM: Free's : 26 free's of 44207405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_997] | 0 | - | 0.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5978bc3caaa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_140] | 0 | - | 0.03 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a949e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.3417088406971257e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_9] | 1 | True | 0.69 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59451a94d810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00017550891966942812 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 397.47 Core Time (ms) : 384.18 TIDL Subgraphs Processing Time (ms) : 384.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 262010724 bytes MEM: Free's : 26 free's of 262010724 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_818] | 0 | - | 0.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6095bb15b760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_329] | 1 | True | 0.11 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61ece8117ad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.870998233999107e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.65 Core Time (ms) : 8.80 TIDL Subgraphs Processing Time (ms) : 8.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25900133 bytes MEM: Free's : 26 free's of 25900133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_1078] | 0 | - | 0.04 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56529aee9a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.0326931637024198e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_889] | 1 | True | 1.63 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56beb3db4560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1254s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00015991419596315785 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1425.35 Core Time (ms) : 1417.41 TIDL Subgraphs Processing Time (ms) : 1417.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 188917709 bytes MEM: Free's : 26 free's of 188917709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_240] | 0 | - | 0.04 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5f768a277d50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 1.7580441746211026e-14 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.24 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_458] | 1 | True | 0.09 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60ae48ee69f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1249s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1250s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00013125030490970143 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.13 Core Time (ms) : 6.00 TIDL Subgraphs Processing Time (ms) : 5.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18131793 bytes MEM: Free's : 26 free's of 18131793 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Convolution_837] | 1 | True | 0.09 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x61d38840f5a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014335863263511043 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.78 Core Time (ms) : 3.67 TIDL Subgraphs Processing Time (ms) : 3.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 17050845 bytes MEM: Free's : 26 free's of 17050845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||